Hi! Could someone briefly tell me the difference between OpenLane(https://github.com/The-OpenROAD-Project/OpenLane) and OpenROAD(https://github.com/The-OpenROAD-Project/OpenROAD) ? I am confused as to which one is a sub-part of which one.

is there a way to export a lef with klayout?

Dear Community, I'm having an issue with OpenSTA: When defining generated_clocks, the report_check command shows the timing from the last generated_clock until the register and omits all the path from the original clock (master clock). Is there a way to enable the report of the whole path from the original clock? For example, in primetime, with the same procedure, the whole path is shown. However, in OpenSTA, the path from the master clock until the last generated_clock is completely omitted. Thank you in advance. Best Regards, Rodrigo Iga #open_sta #sta #static_timing_analysis

Note: No compatibility mode selected! Circuit: ** sch_path: /home/sahana/inverter/xschem/inverter_tb.sch Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 Checking parameters for BSIM 4.5 model x1.xm1:sky130_fd_pr__nfet_01v8__model.25 Fatal: Pclm = -0.0968433 is not positive. Fatal: Drout = -0.261499 is negative. Warning: Cdscd = -0.00649389 is negative. Warning: Eta0 = -0.0934787 is negative. Fatal error: detected during BSIM4v5.5.0 parameter checking for model x1.xm1:sky130_fd_pr__nfet_01v8__model.25 of device instance m.x1.xm1.msky130_fd_pr__nfet_01v8 doAnalyses: no such parameter on this device tran simulation(s) aborted Error: no such vector in in term: v(in) Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 Checking parameters for BSIM 4.5 model x1.xm1:sky130_fd_pr__nfet_01v8__model.25 Fatal: Pclm = -0.0968433 is not positive. Fatal: Drout = -0.261499 is negative. Warning: Cdscd = -0.00649389 is negative. Warning: Eta0 = -0.0934787 is negative. Fatal error: detected during BSIM4v5.5.0 parameter checking for model x1.xm1:sky130_fd_pr__nfet_01v8__model.25 of device instance m.x1.xm1.msky130_fd_pr__nfet_01v8 doAnalyses: no such parameter on this device run simulation(s) aborted ngspice 2 ->

Hello all, I tried to make an ideal opamp in xschem using VCVS with high gain but there was a problem its output is infinite as it has no rails. Is there a way to make a limiter in xschem or is there an Ideal opamp ready to be used?

Hi all. I have downloaded openlane2 as per https://openlane2.readthedocs.io/en/latest/getting_started/common/nix_installation/installation_linux.html. I then try to run an example using: openlane --run-example spm After this it errors out with the following message: PermissionError: [Errno 13] Permission denied: '/home/slice/pdk/SW130/share/pdk/volare' This is most probably due to the fact I havent used volare to install my pdk. Instead it is installed at: /home/slice/pdk/SW130/share/pdk/sky130A I guess I just have to change a pointer to this above path? Is this correct? If so, how do I proceed? Thanks, Diarmuid

This is an ngspice question more than an xschem question. I apologise in advance if it's more appropriate to post on ngspice-users mailing list but I thought I'd have a go here since xschem and ngspice have a fairly close relationship. I'm trying to loop over some tran simulations, each time measuring a frequency and storing away a couple of vectors to eventually plot in the xschem UI. I've attached my spice script (without full netlist) containing the control section. I think that I've followed the advice in the control structure tutorial correctly but executing the script yields "When creating a new vector, it cannot be indexed.", presumably due to the "let" prefix on line "let vecvctl[index] = varvctl" ... I suspect something to do with the dynamic context of where the vectors are being created (the const plot for the initial creation?). Any ideas of how to debug this?

I've just tried the new ngspice42 verilator cosim feature - very nice. Here's the example: https://sourceforge.net/p/ngspice/ngspice/ci/master/tree/examples/xspice/verilator/adc.cir

help me resolve this

Hi everyone, I am running innovus for Sky130 pdk using a riscv processor and openram generated sram memory. We are facing the following issue. Attached are both sky130_tech.lef files and sram_tech.lef files. Can someone help us out ?