@Stefan Schippers is there any functionality in xschem, which permits to validate device parameters ? I mean to check if ie. W of a transistor is within certain range Wmin and Wmax

After 15 months since the announcement: what is the status of sky-S90? Any timeline? (we know that sky-RH90 is subject to strict ITAR rules and therefore cannot be open source)

Is It possible to submit design into new SKY90-FD 90nm? If so, how can I do that? Thank you

Do anyone know how could I perform harmonic balance simulations using xyce in xschem? I'm designing a RF amplifier and I need to have its compression point :/

Hi Everyone I want to use skywater130 .lib file for the yosys command "abc -liberty technology.lib". technology.lib is the dummy name I am using here. Can anyone please let me know from where I will get this file? Thanks

Hi, I run into an error below while trying to run iverilog simulation, /caravel_user_project/caravel/verilog/rtl/caravel_netlists.v41 Include file libs.ref/sky130_fd_io/verilog/sky130_ef_io.v not found is it due to wrong versioning of pdk? I installed openlane and built pdks via openlane repository

Hi, I was trying to compile the sky130 64x512_8 SRAM using

sram_compiler.py

and it gave me the following error. I also set

netlist_only = True

. The error is not thrown for lower number of words (eg: 16, 32) but occurs for higher values such as 128, 256. Is this a configuration issue or is this a bug? If it is a config issue, perhaps the example file should be changed.

DELAY: Writing stimulus...
ERROR: file simulation.py: line 605: Could not find bl net in timing paths.

Have anyone had any luck in installing openvaf in Windows? I downloaded MSVC build tools and installed it. But I cannot seem to do anything with the downloaded openvaf_23_5_0_windows_amd64 file (Note the no extension). Should I rename it to openvaf and add .exe? Or somehow build it using build tools? Help will be greatly appreciated

Has anyone ever attempted to make transient spice simulations including noise? If so, I would be very grateful for some exchange!

I understood that in circuit design with standard cells as building blocks, the cells are placed in parallel rows. Also in each row, cells providing logic functions (and, or etc...) are interleaved with tap and decap cells. Tap and decap are used to guard the circuit against latch-up and vdd drop. So in each row there is a tap every X logic cells and a decap every Y logic cells. X and Y are process depended. If my understanding is correct, what are X e Y for Skywater standard cells ?