Hi all. What is the general plan regarding migrating to "fossi-chat"? I signed up just now and don't see a lot of activity on it (only 2 channels created), see below. Is this going to be the new OS discussion platform? If so, will there be a definite date whereby everyone must have moved across by? @Leo Moser: Are you the owner of this effort? Thanks.

I’m encountering a problem with the MOS models and params. I have been using the models

?fet_xxx_nf

, i.e., what I assume are the models which calculate correct areas and perimeters for fingered FETs. I have been using them no problem with numerical values for width and length. But I tried using params as shown in the attached image, and get lots of errors in ngspice. (I know I haven’t enabled multiple fingers yet) ngspice output (there are many similar)

Undefined parameter [len_3p3]
Netlist line no. 26:
 Formula() error.
      |m=1; sd=0; sb=0; sa=0; nf=1; mult=1; l=len_3p3; w=(wid)*1 ; ad=int((1+1)/2)*(wid)*0.29; as=int((1+2)/2)*(wid)*0.29; pd=2*int((1+1)/2)*((wid)+0.29); ps=2*int((1+2)/2)*((wid)+0.29); swx_vth=sw_vth0_sky130_fd_pr__nfet_g5v0d10v5+sw_vth0_sky130_fd_pr__nfet_g5v0d10v5_mc; nrd=0.29/(wid)/1 ; nrs=0.29/(wid)/1 ; swx_nrds=89.1*nf/w+443.5;| : |l|=|len_3p3|

This is the section of the netlist that starts with the offending instance.

XM9 net10 net12 GND GND sky130_fd_pr__nfet_g5v0d10v5 L={LEN_3P3} W='{WID} * 1 ' nf=1 ad='int((1 + 1)/2) * {WID} * 0.29' as='int((1 + 2)/2) * {WID} * 0.29'
+ pd='2*int((1 + 1)/2) * ({WID} + 0.29)' ps='2*int((1 + 2)/2) * ({WID} + 0.29)' nrd='0.29 / {WID} / 1 ' nrs='0.29 / {WID} / 1 ' sa=0
+ sb=0 sd=0 mult=1 m=1
E4 net11 GND ctrl_vds GND 1
Vvds_ctrl ctrl_vds GND {VDS}
Vvgs_ctrl ctrl_vgs GND dc {VGS} ac 1
R1 net11 src_n1p8lvt 1 m=1
R2 net11 src_n1p8 1 m=1
R3 net11 src_n3p3nvt 1 m=1
R5 net11 src_ng5p0d10p5 1 m=1
R6 src_p1p8lvt net5 1 m=1
R7 src_p1p8 net5 1 m=1
R8 src_p1p8hvt net5 1 m=1
R9 src_pg5p0d10p5 net5 1 m=1
**** begin user architecture code

.param WID=0.5
.param LEN_1P8=0.15
.param LEN_PLVT=0.35
.param LEN_3P3=0.5
.param VGS=0.9
.param VDS=0.6
.options sparse
.probe alli

I think I’m using

param

correctly, because other parameters like the voltage source values have been simulating fine. Is there anything special I need to do when parameterizing device model parameters?

Hello, I am experiencing an issue regarding an LVS for an encoder using standard cells. I appears as though, from the immediate lvs report, that there are two extra instances of an nfet and pfet in my circuit 2(Mag spice, or the longer file). However, looking at the spice file for circuit 2, there are no fet instances when looking at the top level subcircuit. I do not know if this issue is because of the use of standard cells and I am missing something, or something else entirely.

I see. So in theory I should be able to use Xyce to run my multi port sp simulations (but just not be able to use the nice QUCS-S interface for it). (I will test all of these theories and write my experience here, still doing some reading before getting started). Is there a tutorial or document to follow to set up all the PDK and EDA tools nicely? Or are all of them setup individually and manually?

@Krzysztof Herman OpenVAF executables were downloaded on my Ubuntu machine but nothing happens when I try to run it. Any suggestions ?

Hi. Is it possible to import a verilog file mapped with

yosys

to standard cells into

xschem

? I have an example where i have mapped a simple counter to the sky130 standard cells, and i want to perform an analog spice simulation in

xschem

. Here is the synthesized counter.

Is there a way to convert a Verilog netlist to SPICE netlist to perform a mixed-signal simulation on a gate level with analog circuitry?

Hi All. I am just looking into the resistor options in SKY130 - the P+ and P- Poly precision resistors. 1.) Both have a 'b' connection to connect the nwell below the resistor (which shields it from substrate noise). Naturally one would connect this to vdd but given that the substrate is vss, it should also be possible to connect this nwell bulk to vss also. I've done this before in a process which allowed it but just want to confirm it is indeed allowed in this process. Can anyone confirm it is? Context of the question is supply rejection as placing the resistor on a vss referred net would favor connecting the bulk to vss also. 2.) Rs of the P+ resistor is 300ohms/sq while that for the P- resistor is 2kohms/sq. This would make the P- resistor more favorable to low power applications w.r.t area. However, Im a little spooked by the below line in the P- resistor documentation: "Electrical and e-test specs are still TBD, once sufficient silicon has been evaluated." Is the P- resistor mature enough to be used or is it still under development? Thanks,

Hi, I was trying to compile the sky130 64x512_8 SRAM using

sram_compiler.py

and it gave me the following error. I also set

netlist_only = True

. The error is not thrown for lower number of words (eg: 16, 32) but occurs for higher values such as 128, 256. Is this a configuration issue or is this a bug? If it is a config issue, perhaps the example file should be changed.

DELAY: Writing stimulus...
ERROR: file simulation.py: line 605: Could not find bl net in timing paths.

How can I generate a pad frame around my design in order to perform full chip simulation?