Hi all. I am trying to use gdsiistl to convert gds files to stl, but it is not sowkring. Is there anyone, who could help out here? Thanks.

Hi All. I am just looking into the resistor options in SKY130 - the P+ and P- Poly precision resistors. 1.) Both have a 'b' connection to connect the nwell below the resistor (which shields it from substrate noise). Naturally one would connect this to vdd but given that the substrate is vss, it should also be possible to connect this nwell bulk to vss also. I've done this before in a process which allowed it but just want to confirm it is indeed allowed in this process. Can anyone confirm it is? Context of the question is supply rejection as placing the resistor on a vss referred net would favor connecting the bulk to vss also. 2.) Rs of the P+ resistor is 300ohms/sq while that for the P- resistor is 2kohms/sq. This would make the P- resistor more favorable to low power applications w.r.t area. However, Im a little spooked by the below line in the P- resistor documentation: "Electrical and e-test specs are still TBD, once sufficient silicon has been evaluated." Is the P- resistor mature enough to be used or is it still under development? Thanks,

Hi, I'm using WSL 2 and ubuntu 22.04 on windows 10, I have an SSH key added at the repositories.efabless.com/settings/ page. Attempting to clone a project from efabless with git clone ssh://git@repositories.efabless.com/<user_name>/<project_name>.git gets an error: 'ssh: connect to host repositories.efabless.com port 22: Connection timed out fatal: Could not read from remote repository. Please make sure you have the correct access rights and the repository exists.' I can clone my own repositories from github using SSH. Trying git clone https://github.com/efabless/<project_name> prompts for github user/password, entering such gets: remote: Support for password authentication was removed on August 13, 2021. remote: Please see https://docs.github.com/get-started/getting-started-with-git/about-remote-repositories#cloning-with-https-urls for information on currently recommended modes of authentication. fatal: Authentication failed for 'https://github.com/efabless.com/<project_name>/'

Hello everyone, I ran into LVS errors when running

make lvs

on the

gcd

design using

sky130hd

platform. Steps to replicate: 1- Install ORFS using docker. 2- Uncomment

DESIGN_CONFIG=./designs/sky130hd/gcd/config.mk

in /flow/Makefile 3- Run

make

4- Run

make lvs

Errors:

ERROR: In /OpenROAD-flow-scripts/flow/platforms/sky130hd/lvs/sky130hd.lylvs: Pin count mismatch between circuit definition and circuit call: 6 expected, got 7 in /OpenROAD-flow-scripts/flow/objects/sky130hd/gcd/base/6_final_concat.cdl, line 11755 in Netlist::read
ERROR: Pin count mismatch between circuit definition and circuit call: 6 expected, got 7 in /OpenROAD-flow-scripts/flow/objects/sky130hd/gcd/base/6_final_concat.cdl, line 11755 in Netlist::read in Executable::execute

This issue seems old but still not solved, right? https://github.com/The-OpenROAD-Project/OpenROAD/issues/1146 Is there a workaround to do LVS? I have tried deleting stuff causing the errors from the .cdl file

flow/objects/sky130hd/gcd/base/6_final_concat.cdl

and I'm left with an LVS error: netlist mismatch. lvs-issue-with-gcd.png

I understood that in circuit design with standard cells as building blocks, the cells are placed in parallel rows. Also in each row, cells providing logic functions (and, or etc...) are interleaved with tap and decap cells. Tap and decap are used to guard the circuit against latch-up and vdd drop. So in each row there is a tap every X logic cells and a decap every Y logic cells. X and Y are process depended. If my understanding is correct, what are X e Y for Skywater standard cells ?

I try to create a Verilog digital component spice netlist to simulate with ngspice. I converted Verilog RTL to Verilog with a power pin using

vlog2Verilog

. Now with Yosys, I would like to convert this file to a spice file with

write_spice

. The steps that i follow are:

yosys

read_liberty -lib sky130_fd_sc_hd__tt_025C_1v80.lib

read_verilog counter.v

synth -top counter

When I run the last cmd I have this error :

3. Executing SYNTH pass.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Analyzing design hierarchy..
Top module:  \counter
ERROR: Module `sky130_fd_sc_hd__dfxtp_1' referenced in module `counter' in cell `_30_' does not have a port named 'VPWR'.

I have integrated 2KB SRAM hardmacro available from PDK path : sky130A/libs.ref/sky130_sram_macros. I see high number of DRC violation reported by magic tool with "Local interconnect spacing < 0.17um (li.3)" Any suggestion on how to manage this ?

Hi all. What is the general plan regarding migrating to "fossi-chat"? I signed up just now and don't see a lot of activity on it (only 2 channels created), see below. Is this going to be the new OS discussion platform? If so, will there be a definite date whereby everyone must have moved across by? @Leo Moser: Are you the owner of this effort? Thanks.

‼️ Important ‼️ Efabless has shutdown operation due to funding challenges: https://efabless.com/notice Given the current circumstances and uncertainties, we (a group of individuals) have decided to set up a new communication platform called FOSSi Chat. FOSSi Chat uses Matrix, an open protocol for decentralised, secure communications that is already the platform of choice for a large number of open source communities. We are currently in the process of reaching out to the FOSSi Foundation to take ownership of FOSSi Chat. Let's make sure the community as a whole finds a new place, please join FOSSi Chat: fossi-chat.org

Hi, I'm a student who just started with IC design. Since the school provides Cadence tools for free, I'm currently using Virtuoso for schematic design and simulation with the Sky130 PDK (currently using

efabless/main

from Github). What I want to simulate is a simple

nfet

simulation, but I keep encountering many errors. Since the Spectre simulator supports both Spectre and Spice, I thought it would work without issue. I know Sky130 is friendly to the open-source tools, but is it intentionally incompatible with Virtuoso? Does anyone have any insights or comments on this? Please share your experiences with getting it to work with Virtuoso. I would greatly appreciate any advice on the Sky130 PDK ecosystem and its compatibility with Cadence tools.