if I want to do gate level simulations with designs that include openram, is there a gatelevel verilog version of openram? I assume not, but I don't know how to proceed without one

I'm trying to run the static timing analysis on the caravel design including our user project area. Right now I'm only focusing on the main clock (no other external IO or reset yet), and just using the modules:

caravel

,

mgmt_core

,

mgmt_protect

, and a "fake"

chip_io

that just forwards clock to clock_core My idea is first check if the wishbone bus and LA meet the timings Here is the WIP repository of the project: https://github.com/mbalestrini/caravel_timing_analysis On the first tests I'm getting HOLD violations between mgmt_core and our user_project_wrapper and it seems I'm also getting HOLD violations inside mgmt_core. If anyone with more experience wants to check the repository to see if the process is correct or if I'm missing something that would be great. (I'm using caravel's mpw-3a tag)

Hello everyone I want to create a blockage at some empty area in my design is it possible to create the blockage and what is command. Can anyone help with this

I've just tried the new ngspice42 verilator cosim feature - very nice. Here's the example: https://sourceforge.net/p/ngspice/ngspice/ci/master/tree/examples/xspice/verilator/adc.cir

I am doing some experimentation with fine grained clock gating and would love to use the openlane flow to test it out. However, I can't find much info about how well supported clock gating is. I tried synthesizing a bunch of registers with a synchronous enable signal, essentially this:

wire ena;
wire[8:0] data;
wire ena_reg;
wire[8:0] data_reg;
always @(posedge clk) begin
    ena_reg <= ena;
end
always @(posedge clk) begin
    if (ena) begin
        data_reg <= data;
    end else begin
        data_reg <= data_reg;
    end
end

Synthesizing this with the default

flow.tcl

generates multiplexers to select the next value, which is not what I want. I have tried the same thing on ice40 FPGAs using yosys and there it correctly does "clock gating" (it uses the enable pins on the registers) Is clock gating like this even supported by openlane? Do I have to turn it on somehow? From searching around I've found that there is a clock gating cell:

sky130_fd_sc_hd__dlclkp_1

but I have no idea how I'd begin to try and use that

Hello. I am currently trying to launch xschem using https://github.com/iic-jku/osic-multitool and am getting the following error.

hayato@DESKTOP-931VA3D:~$ xschem
cd caravel_user_project_analog

^CUse 'exit' to close the program
open_pdks installation: using /home/hayato/pdk
SKYWATER_MODELS: /home/hayato/pdk/sky130A/libs.tech/ngspice
SKYWATER_STDCELLS: /home/hayato/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice
Tcl_AppInit() error: can not execute /usr/local/share/xschem/xschem.tcl, please fix:
invalid command name "image"
tcleval(): evaluation of script: wm withdraw . failed
         : invalid command name "wm"
tcleval(): evaluation of script: tk_messageBox -icon error -type ok -message        {Tcl_AppInit() err 1: can not execute /usr/local/share/xschem/xschem.tcl, please fix:
 invalid command name "image"} failed
         : invalid command name "tk_messageBox"

What I worked on:

cd osic-multitool/

export NGSPICE_VERSION=38

./iic-osic-setup.sh

cd

source iic-init.sh

There is no error on the way, but when xschem is executed after this, the above error appears. If anyone knows how to solve this problem, we would appreciate it if you could let us know.

Hi, I'm creating LEF files from Magic using as reference this repository by @Nickson Jose (thanks Nickson). I've added the property

FIXED_BBOX

and port attributes

class, use

but I have a doubt about some properties it seems were added on the layout [Fig 2] that I don't understand. I found in Magic documentation a description for

LEFclass

and

LEFsource

[Fig 3] but are not clear for me. Same for

LEFsite

. Could anyone help me with them?

Hi, What is a Klayout FEOL error from the precheck? I looked on the reference https://github.com/efabless/mpw_precheck/blob/main/debug_precheck.md#how-to-load-marker-database-files for the errors, but only saw the Klayout drc errors? I checked the klayout_feol_check.xml file as suggested in the precheck log, but I'm unsure how to read it

<?xml version="1.0" encoding="utf-8"?>
<report-database>
 <description>SKY130 DRC runset</description>
 <original-file/>
 <generator>drc: script='/home/connie/mpw_precheck/checks/tech-files/sky130A_mr.drc'</generator>
 <top-cell>user_analog_project_wrapper</top-cell>
 <tags>
 </tags>
 <categories>
  <category>
   <name>dnwell.2</name>
   <description>dnwell.2 : min. dnwell width : 3.0um</description>
   <categories>
   </categories>
  </category>
  <category>

are there any resources to decipher this? Thanks!

Does anyone know of or have a spectre to spice netlist converter ? I tried spectre2spice but couldn't manage to get it installed .

Hi all. I am trying to use gdsiistl to convert gds files to stl, but it is not sowkring. Is there anyone, who could help out here? Thanks.