@Stefan Schippers: Here's a new question for you. I've been working on this CACE system for automatic characterization. It was developed on the Efabless platform years ago when we were using Electric for schematic entry and hadn't heard of xschem. So I was trying to introduce variables and equations into the netlists to be resolved by direct substitution. For the variables I used the usual standard of

${name}

; for the equations I introduced a stack notation with the odd looking variables

${*}

${/}

${+}

${-}

and suchlike; so

${A} ${B} ${+} 2 ${/}

would resolve to

(A+B)/2

. This notation can get rather cumbersome. I think I can replace the whole system with just a call to xschem to generate a netlist if I pass all the variable names to xschem, but I would also need to replace the stack notation stuff. I think it is a straightforward matter of replacing it with calls to

tcleval

. I've attached a schematic for a CACE testbench. How should I write the device parameters with

tcleval

(or any other syntax that works) so that xschem would do the work of variable substitution and produce the output I'm currently doing with python code inside CACE? (FYI, the variable notation on pins is also being handled inside CACE but I do not think this is needed and I can dispense with it altogether).)

So I've been perusing the "CMOS Circuit Design, Layout and Simulation" book and I had some question about the practical implementations of some of the things explained there : • Looking at some differential amplifier, they rely on bias voltages. In a preceding chapter, they do give some example of generating those, but I'm wondering a couple of things: ◦ Can the same bias generator be used for several "blocks" that use the same bias currents (like several diff amps) ? Because it's a rather "large" block in itself, so if it needs repeating each time, that definitely takes space. ◦ Then how do you deal with matching ? My understanding was that the transistor being biased needed to be matched to the corresponding one in the bias generator, but if you share a reference, they might be more appart ... even in the bias generator itself ( look at for instance ), there are many of them sharing the same gate potential and you can't possibly match all of them (makign they close / shared centroid / ... that kind of stuff)

Hello All Any idea on how to run mismatch simulations in ngspice for sky 130 based netlist??

Hello, I get the following "property error" while doing lvs (even if the circuits match uniquely):

There were property errors.
sky130_fd_pr__cap_mim_m3_2:C2 vs. flying_cap_0//unit_cap_360/sky130_fd_pr__cap_mim_m3_2:1:
Property VM in circuit1 has no matching property in circuit2

Any ideas? @Tim Edwards @Stefan Schippers

Hi Everyone I want to use skywater130 .lib file for the yosys command "abc -liberty technology.lib". technology.lib is the dummy name I am using here. Can anyone please let me know from where I will get this file? Thanks

Hi. Is it possible to import a verilog file mapped with

yosys

to standard cells into

xschem

? I have an example where i have mapped a simple counter to the sky130 standard cells, and i want to perform an analog spice simulation in

xschem

. Here is the synthesized counter.

Hi @Stefan Schippers I'm trying to generate this curve using Xschem and ngspice but I couldn't find a way to plot the frequency

Hi all. I am trying to use gdsiistl to convert gds files to stl, but it is not sowkring. Is there anyone, who could help out here? Thanks.

Hi All. I am just looking into the resistor options in SKY130 - the P+ and P- Poly precision resistors. 1.) Both have a 'b' connection to connect the nwell below the resistor (which shields it from substrate noise). Naturally one would connect this to vdd but given that the substrate is vss, it should also be possible to connect this nwell bulk to vss also. I've done this before in a process which allowed it but just want to confirm it is indeed allowed in this process. Can anyone confirm it is? Context of the question is supply rejection as placing the resistor on a vss referred net would favor connecting the bulk to vss also. 2.) Rs of the P+ resistor is 300ohms/sq while that for the P- resistor is 2kohms/sq. This would make the P- resistor more favorable to low power applications w.r.t area. However, Im a little spooked by the below line in the P- resistor documentation: "Electrical and e-test specs are still TBD, once sufficient silicon has been evaluated." Is the P- resistor mature enough to be used or is it still under development? Thanks,

@Stefan Schippers is there any functionality in xschem, which permits to validate device parameters ? I mean to check if ie. W of a transistor is within certain range Wmin and Wmax