@Matt Venn @Anton Maurovic (efabless support) i want to use the LA pins in caraval as follows la118:113 control signal to user area analog_io16 or mprj_io 26 =3.3V analog_io17 or mprj_io 27 =GND VSS TO GND ANALOG_IO12 OR MPRJ_IO 22 =3.3V ANALOG_IO15 OR MPRJ_IO25 =1.8V LA40 DAC_WL_DOWN =low ( user area control signal) LA48 DAC_WL-UP =HIGH ( user area control signal) ANALOG_IO0 OR MPRJ_IO10 OUTPUT .attached is the code but the output is not correct, could u pls help as its my first LA control program

Could anyone give some advice about caravel on IIC-OSIC-TOOLS (docker-container)? I've been using IIC-OSIC TOOLS (non-docker version) and it works well. Now I'm trying docker-version of IIC-OSIC-TOOLS, but I'm stuck at setup. When I try the flow of caravel_user_project, 'make setup' fails with errors below. % cd caravel_user_project % mkdir dependencies % export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src % export PDK_ROOT=$(pwd)/dependencies/pdks % export PDK=sky130B % make test (snip) make[2]: Entering directory '/foss/designs/caravel_user_project/dependencies/openlane_src' Makefile23 warning: undefined variable 'DOCKER_SWAP' Makefile26 warning: undefined variable 'DOCKER_MEMORY' Makefile42 warning: undefined variable 'ROUTING_CORES' /bin/sh: 1: docker: Permission denied make[2]: * [Makefile114 pull-openlane] Error 127 make[2]: Leaving directory '/foss/designs/caravel_user_project/dependencies/openlane_src' make[1]: * [Makefile84 openlane] Error 2 make[1]: Leaving directory '/foss/designs/caravel_user_project/openlane' make: * [Makefile181 openlane] Error 2 I also tried without changing environmental variables (means, OPENLANE_ROOT=/foss/tools/openlane and PDK_TOOR=/foss/pdks), but 'make setup' also stopped due to permission errors in openlane. Other tools, e.g. xschem, klayout, magic, are working, so I think docker-container was installed correctly. OS is Windows 11 and Docker desktop is v.4.17.1.

Hi everyone! On the documentation webpage of sky130 PDK, In device details section, What do these parameters - VTXNL, VTXNN42 etc. mean? In the PDK, I can only find one transistor corresponding to each type while here, there are multiple parameters given. Also where can I find information about such parameters? I tried searching the documentation of sky130 but wasn't able to find any information on these codewords.

Hi, I'm creating LEF files from Magic using as reference this repository by @Nickson Jose (thanks Nickson). I've added the property

FIXED_BBOX

and port attributes

class, use

but I have a doubt about some properties it seems were added on the layout [Fig 2] that I don't understand. I found in Magic documentation a description for

LEFclass

and

LEFsource

[Fig 3] but are not clear for me. Same for

LEFsite

. Could anyone help me with them?

@Stefan Schippers, I was looking to do mixed signal simulation in xschem. I was wondering if there is a way to import verilog(.v) file in xschem or can i create verilog file in xschem and is there any documentation for writing verilog code in xschem??

does the linter also checks for verilog files included in the blackbox? We have openram memories that have delay and hold timing constructs. Verilator is complaining:

[ERROR]: Timing constructs found in the RTL. Please remove them or wrap them around an ifdef. It heavily unrecommended to rely on timing constructs for synthesis.
[ERROR]: Step 0 (verilator_lint_check) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "run_verilator" line 50)
    invoked from within
"run_verilator"
    (procedure "run_verilator_step" line 3)
    invoked from within
"run_verilator_step"} -errorline 1

Hey everyone!! I am trying to do manual macro placement using ORFS. I could see a variable MACRO_PLACEMENT in macro_palce.tcl file. What needs to given to this variable?

Hi @aquiles viza, @Deni Alves, @Gabriel Maranhão, @Jorge Marin, @Atif Khan, @Akira Tsuchiya, and @Junbeom Park. @mehdi and @Boris Murmann would like to meet with the team leaders to discuss the next steps. I sent also an email to each team leader with this information. Can you join the Chipathon 2024 on Thursday 3rd October, at 11 am EST? Please let us know if it fits your schedule. Kind regards,

Can someone help me with the LVS code error? My config file and error description files: [STEP 42] [INFO]: Running LVS (log: ../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/logs/signoff/42-lvs.lef.log)... [ERROR]: There are LVS errors in the design: See '../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/reports/signoff/42-neuron_core_dffram.lvs.rpt' for a summary and '../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/logs/signoff/42-lvs.lef.log' for details. [ERROR]: Step 42 (lvs) failed with error: -code 1 -level 0 -errorcode NONE -errorinfo { while executing "throw_error" (procedure "quit_on_lvs_error" line 13) invoked from within "quit_on_lvs_error -rpt $count_lvs_rpt -log $log" (procedure "run_lvs" line 76) invoked from within "run_lvs" (procedure "run_lvs_step" line 10) invoked from within "run_lvs_step"} -errorline 1

Dear Community, I'm having an issue with OpenSTA: When defining generated_clocks, the report_check command shows the timing from the last generated_clock until the register and omits all the path from the original clock (master clock). Is there a way to enable the report of the whole path from the original clock? For example, in primetime, with the same procedure, the whole path is shown. However, in OpenSTA, the path from the master clock until the last generated_clock is completely omitted. Thank you in advance. Best Regards, Rodrigo Iga #open_sta #sta #static_timing_analysis