Hey everyone!! I am trying to do manual macro placement using ORFS. I could see a variable MACRO_PLACEMENT in macro_palce.tcl file. What needs to given to this variable?

Hi All. I'm running openlane2 on a basic 4b counter and have encountered an error. In dir ~/mydesigns/counter_4b/, I have created the attached config.json and counter_4b.v files, as per the below link: https://openlane2.readthedocs.io/en/latest/getting_started/newcomers/index.html#configuration The flow errors out with the following: --------------------------------------------------------------------------- [065447] ERROR The following error was encountered while running the flow: main.py:163 OpenROAD.GeneratePDN failed with the following errors: [PDN-0185] Insufficient width (18.86 um) to add straps on layer met4 in grid "stdcell_grid" with total strap width 4.9 um and offset 16.32 um. [065447] ERROR OpenLane will now quit. --------------------------------------------------------------------------- Being a newbie to openlane Im not so good at interpreting these errors yet. It appears to have errored out at step 20 - "20-openroad-generatepdn". Any ideas what it is and how to overcome it? Thanks, Diarmuid

Hi all, I'm getting an error when trying to run openlane on a simple version of the caravel_wrapper with the

user_project_wrapper.def

as a template. Openlane is failing at step 4 (IO placement) telling me that there are 416 IO pins (looks about right according to the verilog), but only 28 "positions" (not sure where this number 28 is coming from). If i look at the def. there 1134 lines with the word

PORT

on them so I have no idea why I'm getting this error. Can anyone offer any insight? Thanks in advance.

OpenROAD 6f9b2bb8b808b1bb5831d4525d868212ae50517a 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO]: Reading ODB at '/media/tom/Storage/Linux/repos/projects/openwave-caravel/openwave/cells/caravel/runs/RUN_2023.12.07_19.53.49/tmp/floorplan/3-initial_fp.odb'…
define_corners Typical
read_liberty -corner Typical /home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuD/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_5v00.lib
Using 1e-12 for capacitance...
Using 1e+00 for resistance...
Using 1e-09 for time...
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-06 for power...
Using 1e-06 for distance...
Reading design constraints file at '/openlane/scripts/base.sdc'…
[INFO]: Setting output delay to: 8.0
[INFO]: Setting input delay to: 8.0
[INFO]: Setting load to: 0.07291
[INFO]: Setting clock uncertainty to: 0.25
[INFO]: Setting clock transition to: 0.15
[INFO]: Setting timing derate to: 5.0 %
Found 0 macro blocks.
[ERROR PPL-0024] Number of IO pins (416) exceeds maximum number of available positions (28).
Error: ioplacer.tcl, 51 PPL-0024

hello does anyone know how I can do a mixed signal simulation in xschem?

Hi everybody, Im having an issue with a mixed signal design on the caravan harness when i try to integrate an analog macro in to a digital one. The openlane flow make it trough the step 41 the LVS. But the netlist in 3 nets. on the "41-lvs.lef.log" file the only mismatch i found is this one

Circuit 1 contains 983 devices, Circuit 2 contains 983 devices.
Circuit 1 contains 1005 nets,    Circuit 2 contains 1002 nets. *** MISMATCH ***

Anyone could give some hints of how to solve this?

@Stefan Schippers is there any functionality in xschem, which permits to validate device parameters ? I mean to check if ie. W of a transistor is within certain range Wmin and Wmax

Has anyone ever attempted to make transient spice simulations including noise? If so, I would be very grateful for some exchange!

Is It possible to submit design into new SKY90-FD 90nm? If so, how can I do that? Thank you

Note: No compatibility mode selected! Circuit: ** sch_path: /home/sahana/inverter/xschem/inverter_tb.sch Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 Checking parameters for BSIM 4.5 model x1.xm1:sky130_fd_pr__nfet_01v8__model.25 Fatal: Pclm = -0.0968433 is not positive. Fatal: Drout = -0.261499 is negative. Warning: Cdscd = -0.00649389 is negative. Warning: Eta0 = -0.0934787 is negative. Fatal error: detected during BSIM4v5.5.0 parameter checking for model x1.xm1:sky130_fd_pr__nfet_01v8__model.25 of device instance m.x1.xm1.msky130_fd_pr__nfet_01v8 doAnalyses: no such parameter on this device tran simulation(s) aborted Error: no such vector in in term: v(in) Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 Checking parameters for BSIM 4.5 model x1.xm1:sky130_fd_pr__nfet_01v8__model.25 Fatal: Pclm = -0.0968433 is not positive. Fatal: Drout = -0.261499 is negative. Warning: Cdscd = -0.00649389 is negative. Warning: Eta0 = -0.0934787 is negative. Fatal error: detected during BSIM4v5.5.0 parameter checking for model x1.xm1:sky130_fd_pr__nfet_01v8__model.25 of device instance m.x1.xm1.msky130_fd_pr__nfet_01v8 doAnalyses: no such parameter on this device run simulation(s) aborted ngspice 2 ->

I have integrated 2KB SRAM hardmacro available from PDK path : sky130A/libs.ref/sky130_sram_macros. I see high number of DRC violation reported by magic tool with "Local interconnect spacing < 0.17um (li.3)" Any suggestion on how to manage this ?