Have anyone had any luck in installing openvaf in Windows? I downloaded MSVC build tools and installed it. But I cannot seem to do anything with the downloaded openvaf_23_5_0_windows_amd64 file (Note the no extension). Should I rename it to openvaf and add .exe? Or somehow build it using build tools? Help will be greatly appreciated

StefanSchippers I was trying out one of your comparator design with xschem based on this . but im facing this problem, even though the utile stimuli code and stimule code is same as yours im getting error. I dont know what error I'm facing , im unable to debug it . Please help

Can we only vary W of MOSFET models in xschem? Are there any other parameters we can control?

Hey everyone!! I am trying to do manual macro placement using ORFS. I could see a variable MACRO_PLACEMENT in macro_palce.tcl file. What needs to given to this variable?

Hello everyone, when I try to run openlane flow I get stuck when it tries to run ABC

24.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-su8k8S/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-su8k8S/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-su8k8S/input.blif 
ABC: + read_lib -w /openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.09 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use).  Time =     0.13 sec
ABC: Memory =    7.77 MB. Time =     0.13 sec
ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1").
ABC: + read_constr -v /openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/synthesis/yosys.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_2".
ABC: Setting output load to be 33.442001.
ABC: + read_constr /openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/synthesis/yosys.sdc 
ABC: + fx 
ABC: Abc_NtkFastExtract: Nodes have duplicated fanins. FX is not performed.
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 50000.0 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + fraig_store 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + fraig_restore 
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 50000.0 
ABC: + buffer -N 5 -S 750.0 
ABC: + upsize -D 50000.0 
ABC: Current delay (0.00 ps) does not exceed the target delay (50000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 50000.0 
ABC: + stime -p 
ERROR: ABC: execution of command "/build/bin/yosys-abc -s -f /tmp/yosys-abc-su8k8S/abc.script 2>&1" failed: return code 139.

I can't even understand what the error is. Do you guys have some clue on how to solve it? Thanks in advance for the effort!

Have a question about parasitic extraction. My design flow goes like this: 1. Generate devices in Magic (since it is possible to import a spice circuit directly) 2. Import to klayout and perform layout 3. Import GDS to magic for LVS 4. Extract using netgen magic for parasitic extraction 5. Change port order in the extracted netlist by copying the subcircuit definition from my schematic 6. Simulate extracted layout Is there a way to set the port order in Klayout instead of in magic, or manually?

Has anyone ever attempted to make transient spice simulations including noise? If so, I would be very grateful for some exchange!

Is It possible to submit design into new SKY90-FD 90nm? If so, how can I do that? Thank you

Hello, I was facing some lvs issues regarding mismatch in number of devices in a custom analog block. I used multiple fingers for nmos and pmos transistors, but netgen does not seem to merge the devices correctly, specifically in the netlist generated from magic layout. Could it be be due to permute in source and drain of transistors not happening properly?

Hi all, I have a student who is doing some simple SPICE simulations of buffers meant to drive off-chip signals for 2.5D packages. She tried nangate45 and is consistently getting some odd (at least to me) results. When trying to achieve a beta ratio of 1, she often has to size the pmos to nmos 10:1, whereas I would think it is normally close to 2:1 for most processes. She is probably going to switch to Sky130 and try rerunning simulations, but I recall that there have been issues with the Sky130 spice models in the past for being unrealistic. • Does anyone have any experience in nangate45 and have an idea why the sizing difference might be so large? • Can someone confirm that the spice models for sky130 are realistic and can simulate large buffer chains? Thank you!