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Can someone help me with the LVS code error? My config file and error description files: [STEP 42] [...
# openlane
s
Can someone help me with the LVS code error? My config file and error description files: [STEP 42] [INFO]: Running LVS (log: ../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/logs/signoff/42-lvs.lef.log)... [ERROR]: There are LVS errors in the design: See '../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/reports/signoff/42-neuron_core_dffram.lvs.rpt' for a summary and '../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/logs/signoff/42-lvs.lef.log' for details. [ERROR]: Step 42 (lvs) failed with error: -code 1 -level 0 -errorcode NONE -errorinfo { while executing "throw_error" (procedure "quit_on_lvs_error" line 13) invoked from within "quit_on_lvs_error -rpt $count_lvs_rpt -log $log" (procedure "run_lvs" line 76) invoked from within "run_lvs" (procedure "run_lvs_step" line 10) invoked from within "run_lvs_step"} -errorline 1
42-lvs.lef.log42-neuron_core_dffram.lvs.rptconfig.json
m
steven, can you share this file 
42-neuron_core_dffram.lef.lvs.log
?
but my guess is there are macro’s that aren’t powered.
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Circuit 1 contains 24989 nets,    Circuit 2 contains 24987 nets. *** MISMATCH ***
There are 2 more nets in the layout than in the verilog.
s
42-neuron_core_dffram.lef.lvs.zip
42-neuron_core_dffram.lef.lvs.zip
m
Yup.
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Net: sm/vccd1                              |(no matching net)
  synapse_matrix_design/vccd1 = 1          |
                                           |
Net: sm/vssd1                              |(no matching net)
  synapse_matrix_design/vssd1 = 1          |
The 
synapse_matrix_design
power is not connected. I suggest adding
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"FP_PDN_MACRO_HOOKS": "sm vccd1 vssd1 vccd1 vssd1",
"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
s
Yes, I do not power my macros and designs. because when i powered the macro and my design i received the error
logs.zip
m
The top layer on your macro should be met4. Is that correct?
s
I use the DFFRAM macro of the caravel_mpw-one/ repo (https://github.com/efabless/caravel_mpw-one/blob/master/gds/DFFRAM.gds.gz)
I have fixed the power pin error but I still have LVS. Can you help me fix the remaining errors? Thanks a lot
lvs_error.zip
m
I still see the power as unconnected.
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Net: sm/vccd1                              |(no matching net)                  
  synapse_matrix_design/vccd1 = 1          |                                 
                                           |                                  
Net: sm/vssd1                              |(no matching net)                 
  synapse_matrix_design/vssd1 = 1          |
Can you share your 
config.json
file?
s
config.json
config.json
this is config.json of neuron_core_dffram
and config.json of synapse_matrix_design is
config.json
config.json
lvs_synapse.zip
lvs_synapse.zip
m
sm
is your 
synapse_matrix
right? I expect it needs to be powered with 
FP_PDN_MACRO_HOOKS
in 
neuron_core_dffram/config.json
.
I think all you need to do is connect it to power with 
FP_PDN_MACRO_HOOKS
in 
neuron_core_dffram/config.json
. That might be 3 levels of macros though. You can use up to metal4 in 
neuron_core_dffram
but only up to metal3 in 
synapse_matrix
.
s
Yes. I understand that. But macro RAM256(DFFRAM) is a hard macro I got from (https://github.com/efabless/caravel_mpw-one/blob/master/gds/DFFRAM.gds.gz). So I can't control my synthesis flow.. Can you help me rewrite config.json from config.tcl(https://github.com/efabless/caravel_mpw-one/blob/master/openlane/DFFRAM/config.tcl)? I tried but got an error right at Step1: unmapped cells
m
You can use 
RAM256
as a hard macro. Can you share your repo? I’m having trouble understanding what you’re trying to do.
s
This is the repo I used to build DFFRAM
m
That looks like it will create a macro that you can use in the top level of your design. If you want to use it at a lower level, you might need to reduce the max routing layer. I still don’t see your full hierarchy. Can you share your top level repo?
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