Hi everybody, Im having an issue with a mixed signal design on the caravan harness when i try to integrate an analog macro in to a digital one. The openlane flow make it trough the step 41 the LVS. But the netlist in 3 nets. on the "41-lvs.lef.log" file the only mismatch i found is this one

Circuit 1 contains 983 devices, Circuit 2 contains 983 devices.
Circuit 1 contains 1005 nets,    Circuit 2 contains 1002 nets. *** MISMATCH ***

Anyone could give some hints of how to solve this?

Hello everyone I want to create a blockage at some empty area in my design is it possible to create the blockage and what is command. Can anyone help with this

Hello guys, i have two file "lef" and "def", how can i visualize them in magic? I tried both command, "lef ready <file>" and "def ready <file>", but i get this error...

I am doing some experimentation with fine grained clock gating and would love to use the openlane flow to test it out. However, I can't find much info about how well supported clock gating is. I tried synthesizing a bunch of registers with a synchronous enable signal, essentially this:

wire ena;
wire[8:0] data;
wire ena_reg;
wire[8:0] data_reg;
always @(posedge clk) begin
    ena_reg <= ena;
end
always @(posedge clk) begin
    if (ena) begin
        data_reg <= data;
    end else begin
        data_reg <= data_reg;
    end
end

Synthesizing this with the default

flow.tcl

generates multiplexers to select the next value, which is not what I want. I have tried the same thing on ice40 FPGAs using yosys and there it correctly does "clock gating" (it uses the enable pins on the registers) Is clock gating like this even supported by openlane? Do I have to turn it on somehow? From searching around I've found that there is a clock gating cell:

sky130_fd_sc_hd__dlclkp_1

but I have no idea how I'd begin to try and use that

Hi there, I'm running into the following error when simulating a synthesized design with ngspice (netlist attached)...

tom@tom:~/repos/projects/openwave$ ngs pll tb_pfd
setup_tcp_xschem: problems listening to TCP port: 2021
couldn't open socket: address already in use


Note: Compatibility modes selected: hs a

Warning: m=xx on .subckt line will override multiplier m hierarchy!


Circuit: 

Error: unknown subckt: x1.xfiller_13_144.x0 vdd x1.xfiller_13_144.a_124_375# x1.xfiller_13_144.a_36_472# vdd x1.xfiller_13_144.pfet_06v0 <http://x1.xfiller_13_144.ad|x1.xfiller_13_144.ad>=1.0736p x1.xfiller_13_144.pd=6.64u <http://x1.xfiller_13_144.as|x1.xfiller_13_144.as>=0.5368p <http://x1.xfiller_13_144.ps|x1.xfiller_13_144.ps>=3.32u x1.xfiller_13_144.w=1.22u l=1u
    Simulation interrupted due to error!

Note: No ".plot", ".print", or ".fourier" lines; no simulations run

I have the following included in my top level spice dec but it still seems to be unable to find the 6v fets as far as i can tell

.include "/home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuC/libs.tech/ngspice/design.ngspice"
.lib "/home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuC/libs.tech/ngspice/sm141064.ngspice typical
.lib "/home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuC/libs.tech/ngspice/smbb000149.ngspice typical"

Anyone have any ideas? Thanks in advance, Tom

Hi! 1. What are the typical use cases for utilizing APB over AHB and vice versa? 2. What determines selection of AXI over APB/AHB? Is it just operating frequency or are there some other parameters? At what frequency does we use APB, then AHB and then AXI? 3. Why do we use bridges and not use AXI all over with some modifications like using AXI-Lite where required? I have gone through their specs but haven't really found satisfactory answers to the above or, I could have missed them. Would really help if someone answers it here! Thanks, in advance!

Does anyone know of or have a spectre to spice netlist converter ? I tried spectre2spice but couldn't manage to get it installed .

I see. So in theory I should be able to use Xyce to run my multi port sp simulations (but just not be able to use the nice QUCS-S interface for it). (I will test all of these theories and write my experience here, still doing some reading before getting started). Is there a tutorial or document to follow to set up all the PDK and EDA tools nicely? Or are all of them setup individually and manually?

Hi We are working on mixed signal design. We have a digital Macro and integrate it into user analog project wrapper along with our analog design in magic and manually do the routing , finally generate spice file and gds. How we can incorporate our digital design into xschem for the purpose of LVS in precheck?

Have anyone had any luck in installing openvaf in Windows? I downloaded MSVC build tools and installed it. But I cannot seem to do anything with the downloaded openvaf_23_5_0_windows_amd64 file (Note the no extension). Should I rename it to openvaf and add .exe? Or somehow build it using build tools? Help will be greatly appreciated