Hello everyone, I ran into LVS errors when running

make lvs

on the

gcd

design using

sky130hd

platform. Steps to replicate: 1- Install ORFS using docker. 2- Uncomment

DESIGN_CONFIG=./designs/sky130hd/gcd/config.mk

in /flow/Makefile 3- Run

make

4- Run

make lvs

Errors:

ERROR: In /OpenROAD-flow-scripts/flow/platforms/sky130hd/lvs/sky130hd.lylvs: Pin count mismatch between circuit definition and circuit call: 6 expected, got 7 in /OpenROAD-flow-scripts/flow/objects/sky130hd/gcd/base/6_final_concat.cdl, line 11755 in Netlist::read
ERROR: Pin count mismatch between circuit definition and circuit call: 6 expected, got 7 in /OpenROAD-flow-scripts/flow/objects/sky130hd/gcd/base/6_final_concat.cdl, line 11755 in Netlist::read in Executable::execute

This issue seems old but still not solved, right? https://github.com/The-OpenROAD-Project/OpenROAD/issues/1146 Is there a workaround to do LVS? I have tried deleting stuff causing the errors from the .cdl file

flow/objects/sky130hd/gcd/base/6_final_concat.cdl

and I'm left with an LVS error: netlist mismatch. lvs-issue-with-gcd.png

So I've been perusing the "CMOS Circuit Design, Layout and Simulation" book and I had some question about the practical implementations of some of the things explained there : • Looking at some differential amplifier, they rely on bias voltages. In a preceding chapter, they do give some example of generating those, but I'm wondering a couple of things: ◦ Can the same bias generator be used for several "blocks" that use the same bias currents (like several diff amps) ? Because it's a rather "large" block in itself, so if it needs repeating each time, that definitely takes space. ◦ Then how do you deal with matching ? My understanding was that the transistor being biased needed to be matched to the corresponding one in the bias generator, but if you share a reference, they might be more appart ... even in the bias generator itself ( look at for instance ), there are many of them sharing the same gate potential and you can't possibly match all of them (makign they close / shared centroid / ... that kind of stuff)

Hello, I get the following "property error" while doing lvs (even if the circuits match uniquely):

There were property errors.
sky130_fd_pr__cap_mim_m3_2:C2 vs. flying_cap_0//unit_cap_360/sky130_fd_pr__cap_mim_m3_2:1:
Property VM in circuit1 has no matching property in circuit2

Any ideas? @Tim Edwards @Stefan Schippers

Hi, does Klayout have a dark mode? I am trying to use the SKY 130 PDK and its a bit hard to see things in the default light mode

Hi, I'm using WSL 2 and ubuntu 22.04 on windows 10, I have an SSH key added at the repositories.efabless.com/settings/ page. Attempting to clone a project from efabless with git clone ssh://git@repositories.efabless.com/<user_name>/<project_name>.git gets an error: 'ssh: connect to host repositories.efabless.com port 22: Connection timed out fatal: Could not read from remote repository. Please make sure you have the correct access rights and the repository exists.' I can clone my own repositories from github using SSH. Trying git clone https://github.com/efabless/<project_name> prompts for github user/password, entering such gets: remote: Support for password authentication was removed on August 13, 2021. remote: Please see https://docs.github.com/get-started/getting-started-with-git/about-remote-repositories#cloning-with-https-urls for information on currently recommended modes of authentication. fatal: Authentication failed for 'https://github.com/efabless.com/<project_name>/'

Hi! 1. What are the typical use cases for utilizing APB over AHB and vice versa? 2. What determines selection of AXI over APB/AHB? Is it just operating frequency or are there some other parameters? At what frequency does we use APB, then AHB and then AXI? 3. Why do we use bridges and not use AXI all over with some modifications like using AXI-Lite where required? I have gone through their specs but haven't really found satisfactory answers to the above or, I could have missed them. Would really help if someone answers it here! Thanks, in advance!

Hello everyone, when I try to run openlane flow I get stuck when it tries to run ABC

24.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-su8k8S/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-su8k8S/abc.script".
ABC: 
ABC: + read_blif /tmp/yosys-abc-su8k8S/input.blif 
ABC: + read_lib -w /openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/trimmed.lib 
ABC: Parsing finished successfully.  Parsing time =     0.09 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use).  Time =     0.13 sec
ABC: Memory =    7.77 MB. Time =     0.13 sec
ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1").
ABC: + read_constr -v /openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/synthesis/yosys.sdc 
ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_2".
ABC: Setting output load to be 33.442001.
ABC: + read_constr /openlane/designs/mydesign/runs/RUN_2021.12.12_20.21.59/tmp/synthesis/yosys.sdc 
ABC: + fx 
ABC: Abc_NtkFastExtract: Nodes have duplicated fanins. FX is not performed.
ABC: + mfs 
ABC: + strash 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + retime -D -D 50000.0 -M 5 
ABC: + scleanup 
ABC: Error: The network is combinational.
ABC: + fraig_store 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + balance 
ABC: + rewrite 
ABC: + refactor 
ABC: + balance 
ABC: + rewrite 
ABC: + rewrite -z 
ABC: + balance 
ABC: + refactor -z 
ABC: + rewrite -z 
ABC: + balance 
ABC: + fraig_store 
ABC: + fraig_restore 
ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 
ABC: + retime -D -D 50000.0 
ABC: + buffer -N 5 -S 750.0 
ABC: + upsize -D 50000.0 
ABC: Current delay (0.00 ps) does not exceed the target delay (50000.00 ps). Upsizing is not performed.
ABC: + dnsize -D 50000.0 
ABC: + stime -p 
ERROR: ABC: execution of command "/build/bin/yosys-abc -s -f /tmp/yosys-abc-su8k8S/abc.script 2>&1" failed: return code 139.

I can't even understand what the error is. Do you guys have some clue on how to solve it? Thanks in advance for the effort!

Hi, "Node libs/gui/xopendisplay/cflags is required but provided detection callback fails to find that feature on system".. this is the error iam getting while trying to compile xschem. Iam using ubuntu 20.04. Any help?

@Stefan Schippers I am trying to do a basic parametric sweep (snapshot attached). In the waveform graph, how to differentiate between the traces? i.e., how to show the parameter associated with every VOUT trace? Also for the cursors, how to jump from one VOUT trace to another? Is this explained in xschem manual? I couldn't find this.

I understood that in circuit design with standard cells as building blocks, the cells are placed in parallel rows. Also in each row, cells providing logic functions (and, or etc...) are interleaved with tap and decap cells. Tap and decap are used to guard the circuit against latch-up and vdd drop. So in each row there is a tap every X logic cells and a decap every Y logic cells. X and Y are process depended. If my understanding is correct, what are X e Y for Skywater standard cells ?