https://open-source-silicon.dev
Join Slack
Hello all, I am working on a CMOS voltage reference design for chipalooza, time is getting short and...
# analog-design
a
Hello all, I am working on a CMOS voltage reference design for chipalooza, time is getting short and my op simulations are getting unstable 😕 my work is here (https://github.com/adankvitschal/sky130_ak_ip__cmos_vref) in case anyone would like to take a look (altough current circuit is not commited yet, just the core part) 1. Just looking at these outputs, can anyone say if the problem is with simulation parameters or circuit startup? (there are vref vs temp and vref vs supply). The problems started when I added a 1M resitor and 0.1pf capacitor as a load at vref output. 2. Also, I am having a hard time finding a decent technique to generate scaled versions of my reference voltage, should I just use gigantic resitors for this? my current budget is around 1uA, so, R>1M, is this ok?
s
May be your vref circuit does not have a dc startup, I see the C1 capacitor is used to do a startup of the circuit when ramping up Vdd, however in DC the situation below is a possible (meta stable? ) state and it locks out the vref to 0V. in the image: red = Vdd, blue = 0V, cyan=whatever.
t
@Adan Kvitschal: The high-value poly resistor is 2000 ohms/square and so > 1Mohm resistors are feasible without taking up a ridiculous amount of area; 1 Mohm is only 500 squares.
@Adan Kvitschal: I think the problem here is one that is inherent to bandgaps or any circuit that has metastable operating points. Due to the metastable states, a DC or AC analysis may come up randomly in any state that it deems stable. A startup circuit won't help because the analysis isn't transient. Once choice is to replace the DC analysis with an equivalent transient analysis---In this case, run a transient simulation through startup and then make the measurement. The characterization will take longer, but it will be guaranteed to be in the correct state at the time the measurement is made. The other choice is to try to find some initial condition to apply to the DC analysis to force it into the correct state. You would still need at least one transient analysis to show that the startup circuit works.
c
@Adan Kvitschal, please change the absolute path
Copy code
-C {/home/moduhub/work/sky130_ak_ip__cmos_vref/xschem/sky130_ak_ip__cmos_vref.sym} 10 40 0 0 {name=X1}
+C {xschem/sky130_ak_ip__cmos_vref.sym} 10 40 0 0 {name=X1}
in all your 
cace/tb_*.sch
schematics, and expect to route out the Vbp pmos gate voltage to M7, M8, M9 to a bias distribution block with transistors (and branch currents) that match the current in M8.
@Adan Kvitschal, for clarification, here's a screenshot of my 
gitk --all
.
@Adan Kvitschal, I'll start messing with 
.NODESET
[ https://ngspice.sourceforge.io/docs/ngspice-html-manual/manual.xhtml#subsec__NODESET ] in your 
.DC
schematics, once I have sufficiently understood how to write CACE compatible 
cace/tb_<expletive deleted>.sch
test schematics, so the Powers That Beâ„¢ won't eliminate me in the schematic design review phase, based on the assumption that detailed building block interface specifications make sense and Must. Be. Followed. And. Documented. at this time.
a
Thank you all for the support, I am going through all the information here as fast as I can, but unfortunatelly I wiill only be able to give proper responses in around 5h from now due to my work schedule. I might commit my work in progress here in around and hour, but it is getting kind of messy since I am trying to add a buffer stage in the output
@Christoph Maier i wasn't aware the absolute paths were getting in there, will fix, thanks. About the current mirrors am not very sure, I should route the gate voltage out of the vref block as a pin or maybe just redraw the bias block and make connections using net names for clarity? M7 and M8 are mirroring the same current, but the M9 branch is 1:10, about the bulk/body voltages there was an issue before but I am simulating without the enable transistor, every p bulk tied to avdd. Feel free to point out any information I might be getting wrong, any help will be appreciated.
c
@Adan Kvitschal, what name do you want to give the net connecting to the bottom plate of 
C1
, connecting to the gate of 
M11
in your 
sky130_ak_ip__cmos_vref.sch
schematic? It needs a name if we want to 
.NODESET
it to 
avdd
.
@Adan Kvitschal, in about 5…6 hours from now (i.e., some 2…3 hours later than you), I could make time to do something like what Software Suits call "pair programming": I'd push my fork of your 
sky130_ak_ip__cmos_vref
onto a github of mine, you could give me a crash course how to circumnavigate undocumented inconsistencies in the open source tool chain, i.e., 
xschem
, 
ngspice
, and, most unpredictably of all, 
cace
, and we go over your voltage reference design, maybe compare notes from my last attempt to get through a quagmire of inconsistent design tools, https://github.com/MastellaM/sky130_TAC3/pull/3 , in particular 
OgueyAebischer.sch
and 
ToBiasStartup.sch
, while I actually start to put my ideas about a bias block from inside my head and the 
transistorcharacterization
branch of https://bitbucket.org/cmucsd/transistorcharacterization/src/master/ into a 
sky130_cm_ip__bias
"IP" repository. Would that make sense for you? If so, please shoot me an email to cm.hardware.software.elsewhere@gmail.com, because for the next few hours, I may be away from efabless slack, but the email will reach me through my cell phone.
👀 1
s
@Adan Kvitschal a possible DC startup (alternative as the transient capacitor assisted startup) is the following. Mstartup will pull the current source gates low if circuit is in the off meta-state, and will self-switch off when startup is completed. This transistor will remove the off-state from quasi-stable meta states.
👀 1
a
@Stefan Schippers I will test this here too in about an hour, did you add Rload to vref? I think I wont be able to fulfill load regulation without an additional buffer, anyway, in this case Rload would be placed elsewhere. Maybe R insn't a good model for the load also..
t
For a bandgap, the load is usually given as a current.
a
Assuming I should put a current source as the load, wouldn't that power the circuit or even change psrr and other figures?
t
The way I did it a while ago for the X-Fab design challenge we did, a current load was specified only for the load regulation testbench. Testbenches like PSRR used a resistive load.
✅ 2
l
You could try connecting M11 source to M10 gate. Maybe add another start-up switch in parallel to M11, but with its source connected to vref also. This may be the problem why it has problems with start up. You could also lower gmin using .option gmin=1e-9. Default is 1e-12. Another solution is to use .option rshunt=1e12. See the references in ngspice manual. For your DC sim, try making a negative sweep, starting at the max voltage and decreasing it. Not related to this issue, you should use you trimming switches connected to the drain terminals, not source. Their switches' ron can cause trouble.
https://ltwiki.org/index.php?title=Convergence_problems%3F Don't forget to run a transient simulation with no DC initial conditions to check if your circuit is starting up by itself. As a last resort, if your circuit does start with transient sims, you can run an optran sim. Check that on the ngspice manual.
c
As for precise scaling of voltages, is there any other feasible way than a switched capacitor amplifier? If not, that would be a realistic load on the currently existing Vref. … which opens a can of worms that can be closed by final design review, but not until tomorrow night.
a
@Luis Henrique Rodovalho Thank you for the pointers, I am experimenting with some of them right now. About the trimming, that circuit was just a guess, I was about to ask someone for suggestions there too. Do you mean I should swap them like this?
I am preparing a "design" version of the schematics to fill it with some current probes. I dont think this will export well to magic, so I am keeping a separate file to help with quick simulations outside of cace.
c
@Adan Kvitschal, I pushed something to your fork … and I'm wondering if a "device under test" schematic separate from the testbenches is required by cace. It should be possible to measure the source currents without requiring vmeas elements.
s
@Adan Kvitschal any device used in xschem can be disabled or shorted for LVS. If you set the 
lvs_ignore
flag (
Simulation->LVS -> set lvs_ignore variable
) all components that have a 
lvs_ignore=short
will propagate the same nodal information on all ports, if 
lvs_ignore=open
or 
lvs_ignore=1
is given it will be removed from the netlist. If you need back a simulation netlist uncheck 
lvs_ignore
flag and you get your ammeters back. In below image the shorted ammeter is displayed in red, the open ammeter in grey. You can use this to short any component or delete components that are used only for simulation porposes and do not correspond to matching silicon devices.
a
@Stefan Schippers This is a nice trick, I will try to reintegrate the schematics later using this option
Ok, so just to close this up, I have a sad confession to do. I was using this as a load:
Copy code
name=R1
value=1M
I totally forgot that this is a 0.001 ohms resistor, not a 1M resistor. I know ngspice uses 1Meg for this, just forgot. Simulations are back on track, and my circuit even gained a relatively complex output buffer, which might prove necessary to meet load regulation specs, so, ok. I am commiting the working circuit as a separate schematic in /xschem, will try to integrate with cace again tomorrow in case anyone is following. Thanks for all the help, I am a big fan of this community.
l
Yep, @Adan Kvitschal . The trimming switches should be placed like that in your circuit.
✅ 1
a
Just for completeness, maybe other spice non-experts like me might benefit from the information. Apart from the 1M resistor, there were also some dangling components in different places preventing simulation from converging, in yet another case there was a capacitor with one of the terminals open. Just deleted them and got everything working again.
39 Views
Open in Slack
PreviousNext
Powered by

What is Linen?

Linen is a search-engine friendly community platform. We offer integrations with existing Slack/Discord communities and make those conversations Google-searchable.

Powered by