Hello, I was facing some lvs issues regarding mismatch in number of devices in a custom analog block. I used multiple fingers for nmos and pmos transistors, but netgen does not seem to merge the devices correctly, specifically in the netlist generated from magic layout. Could it be be due to permute in source and drain of transistors not happening properly?

New Fet parameter annotator is added in sky130. Shows

gm, gds, vth, vdsat, cgg, cgdo, cgso

and

ft

, calculated as

ft = gm / [2π (Cgg + Cgdo + Cgso)]

All the necessary procedures are in the sky130

xschemrc

file, since all this is pdk-specific (plus the

sky130_fd_pr/annotate_fet_params.sym

symbol). Next step is to add similar functionality for the IHP PDK if there interest. @Harald Pretl I have verified thet the

ft

calculated with the above formula is correct (of course i was not questioning the formula but the ngspice

cg*

parameters), i have run an AC analysis and let ngspice show the point where unity current gain occurs. The frequency value matches with the formula as shown in the video.

Hello everyone, I've just integrated analog macro (OpAmp) into caravel (user_project_wrapper), providing GDS, LEF, SPICE (generated from xschem, copied to spi/lvs subdirectory), Verilog stub. Everything is fine while hardening user_project_wrapper (= flow is successfull, including LVS) and resulting GDS looks as expected. However, during precheck LVS is failing. According to "lvs.report", everything seems to be ok (screenshot included).

Cell pin lists are equivalent.

Device classes user_project_wrapper and user_project_wrapper are equivalent.

"lvs.log" states that:

circuit opamp_cascode contains no devices.

and there's a warning:

Warning: device level LVS may be incomplete due to 1 unflattened cell(s)

However, everything seems to be totally fine, because:

Circuits match uniquely.

On the other hand, "LVS_check.log" states that, for analog macro:

Circuit 1 contains 98 devices, Circuit 2 contains 98 devices.

Circuit 1 contains 4605 nets,    Circuit 2 contains 6017 nets. *** MISMATCH ***

Final result:

Top level cell failed pin matching.

In "soft.report", I see some mismatches (example screenshot included).

Hi there, I'm running into the following error when simulating a synthesized design with ngspice (netlist attached)...

tom@tom:~/repos/projects/openwave$ ngs pll tb_pfd
setup_tcp_xschem: problems listening to TCP port: 2021
couldn't open socket: address already in use


Note: Compatibility modes selected: hs a

Warning: m=xx on .subckt line will override multiplier m hierarchy!


Circuit: 

Error: unknown subckt: x1.xfiller_13_144.x0 vdd x1.xfiller_13_144.a_124_375# x1.xfiller_13_144.a_36_472# vdd x1.xfiller_13_144.pfet_06v0 <http://x1.xfiller_13_144.ad|x1.xfiller_13_144.ad>=1.0736p x1.xfiller_13_144.pd=6.64u <http://x1.xfiller_13_144.as|x1.xfiller_13_144.as>=0.5368p <http://x1.xfiller_13_144.ps|x1.xfiller_13_144.ps>=3.32u x1.xfiller_13_144.w=1.22u l=1u
    Simulation interrupted due to error!

Note: No ".plot", ".print", or ".fourier" lines; no simulations run

I have the following included in my top level spice dec but it still seems to be unable to find the 6v fets as far as i can tell

.include "/home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuC/libs.tech/ngspice/design.ngspice"
.lib "/home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuC/libs.tech/ngspice/sm141064.ngspice typical
.lib "/home/tom/repos/edalibs/pdks/gf180mcu/gf180mcuC/libs.tech/ngspice/smbb000149.ngspice typical"

Anyone have any ideas? Thanks in advance, Tom

Hello, Does anyone know if I can do a parametric sweep on ngspice similar to cadence?

Dear all, can OpenLane work with VHDL-based source files? or I have to convert all VHDL files to Verilog? If so, are there any recommended VHDL-->Verilog converters? Thanks. Anas

I try to create a Verilog digital component spice netlist to simulate with ngspice. I converted Verilog RTL to Verilog with a power pin using

vlog2Verilog

. Now with Yosys, I would like to convert this file to a spice file with

write_spice

. The steps that i follow are:

yosys

read_liberty -lib sky130_fd_sc_hd__tt_025C_1v80.lib

read_verilog counter.v

synth -top counter

When I run the last cmd I have this error :

3. Executing SYNTH pass.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Analyzing design hierarchy..
Top module:  \counter
ERROR: Module `sky130_fd_sc_hd__dfxtp_1' referenced in module `counter' in cell `_30_' does not have a port named 'VPWR'.

Can we only vary W of MOSFET models in xschem? Are there any other parameters we can control?

Hi Everyone I want to use skywater130 .lib file for the yosys command "abc -liberty technology.lib". technology.lib is the dummy name I am using here. Can anyone please let me know from where I will get this file? Thanks

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