Hi. Is it possible to import a verilog file mapped with

yosys

to standard cells into

xschem

? I have an example where i have mapped a simple counter to the sky130 standard cells, and i want to perform an analog spice simulation in

xschem

. Here is the synthesized counter.

If you just want to simulate you should write the synthetized netlist to spice format. if you want to use xschem the best thing to do is to create a symbol with the I/O pins of the counter and link to the spice netlist. The following picture is an example of a symbol for the NE555 IC. Only the symbol is drawn (with some artwork) with the NE555 I/O/Supply pins. A

spice_sym_def

attribute is defined to include a text file for the NE555 netlist obtained from a vendor.

Thanks Stefan! I saw your tutorial with the 555 example. So i was think about doing it that way. But I ran into the problem with the missing power pins, when using

write_spice

in

yosys

. So I'll try the guide you linked 🙂