Hi, I am trying to run OpenROAD-flow-scripts in a native Ubuntu 22.04, but am continuously encountering the following error, any idea how to fix this? I have downloaded yosys and klayout as well as openroad and all of them are building and working fine. But when I try to make the flow script Makefile, I am encountering this particular error. I tried to change paths for yosys, but its still persistent.

Hi, does Klayout have a dark mode? I am trying to use the SKY 130 PDK and its a bit hard to see things in the default light mode

お初の方もいらっしゃると思うので、自作ツールの紹介をさせてください。 設定レジスタ (CSR) の RTL などを、レジスタマップから自動生成するツールを作っています。 https://github.com/rggen/rggen 対応するレジスタマップのフォーマットは以下の通りです。 • JSON • TOML • YAML • Ruby • Sifive DuH • スプレッドシート (MS Excel, Libreoffice Calc, CSV) これらのフォーマットで記述したレジスタマップから、以下のファイルを生成します。 • RTL (SV/Verilog/VHDL) ◦ APB/AXI4 Lite/Wishbone に対応 • UVM RAL model • C header file • Markdown 例えば、以下のレジスタマップから、 • https://github.com/rggen/rggen-sample/blob/master/block_0.ym • https://github.com/rggen/rggen-sample/blob/master/block_0.toml • https://github.com/rggen/rggen-sample/blob/master/block_0.rb • https://github.com/rggen/rggen-sample/blob/master/block_0.xlsx l 以下の生成物を、生成することができます。 • https://github.com/rggen/rggen-sample/blob/master/block_0.sv • https://github.com/rggen/rggen-sample/blob/master/block_0.v • https://github.com/rggen/rggen-sample/blob/master/block_0.vhd • https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv • https://github.com/rggen/rggen-sample/blob/master/block_0.h • https://github.com/rggen/rggen-sample/blob/master/block_0.md MIT ライセンスで公開している OSS なので、趣味商用問わず無償で利用可能です。 機会があれば、見てみてください。

Can someone help. I am facing LVS mismatch issue when I run user_project_wrapper.v but when I run user_proj_example.v there's no issue of LVS. Thanks in advance.

Duplicating this error message, because apparently the ngspice

plot

instruction cannot handle lines of a bus, although

display

can handle signals like

io_out[11]

just fine.

Hey, I am trying to set up Cadence EMX with the Sky130 Cadence PDK; has anyone made the .proc file with the process stack information used for setting up EMX?

Hello. I tried to put macros into my project. I have finished placing the macros and setting up the config.json. I proceed to run openlane for synthesis and tapeout. I get a Running Global Routing error code. Specifically, the error: [ERROR GRT-0119] Routing congestion too high. Check the congestion heatmap in the GUI and load /home/edabk/efabless/caravel_user_project/openlane/neuron_core_dffram/runs/23_11_28_11_46/tmp/routing/groute-congestion.rpt in the DRC viewer.

Hmm... in various points throughout my build I've gotten the following warnings at the end: • There are max slew violations in the design at the typical corner • There are max capacitance violations in the design at the typical corner • There are max fanout violations in the design at the typical corner What would be a good way to address each of these issues? More specifically, what knobs should I be adjusting in the configuration file for each warning?

Hello, all. During LVS, there is an error as below. How can I solve this problem? RuntimeError: Can't find a schematic counterpart for the top cell current_cell_1X - use 'same_circuit' to establish a correspondence in Executable

How to check temperature variation in xschem? I am designing BGR.