Hi! Can someone please help me with the following?

Using IHP SG13G2 open PDK and klayout. Does anyone know how to get rid of this active filler area, density, global metal drc errors??? I've been trying different area and filling them but this ertror won't go. Slack Conversation

@Stefan Schippers, I was looking to do mixed signal simulation in xschem. I was wondering if there is a way to import verilog(.v) file in xschem or can i create verilog file in xschem and is there any documentation for writing verilog code in xschem??

Hello, all. During LVS, there is an error as below. How can I solve this problem? RuntimeError: Can't find a schematic counterpart for the top cell current_cell_1X - use 'same_circuit' to establish a correspondence in Executable

Could anyone give some advice about caravel on IIC-OSIC-TOOLS (docker-container)? I've been using IIC-OSIC TOOLS (non-docker version) and it works well. Now I'm trying docker-version of IIC-OSIC-TOOLS, but I'm stuck at setup. When I try the flow of caravel_user_project, 'make setup' fails with errors below. % cd caravel_user_project % mkdir dependencies % export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src % export PDK_ROOT=$(pwd)/dependencies/pdks % export PDK=sky130B % make test (snip) make[2]: Entering directory '/foss/designs/caravel_user_project/dependencies/openlane_src' Makefile23 warning: undefined variable 'DOCKER_SWAP' Makefile26 warning: undefined variable 'DOCKER_MEMORY' Makefile42 warning: undefined variable 'ROUTING_CORES' /bin/sh: 1: docker: Permission denied make[2]: * [Makefile114 pull-openlane] Error 127 make[2]: Leaving directory '/foss/designs/caravel_user_project/dependencies/openlane_src' make[1]: * [Makefile84 openlane] Error 2 make[1]: Leaving directory '/foss/designs/caravel_user_project/openlane' make: * [Makefile181 openlane] Error 2 I also tried without changing environmental variables (means, OPENLANE_ROOT=/foss/tools/openlane and PDK_TOOR=/foss/pdks), but 'make setup' also stopped due to permission errors in openlane. Other tools, e.g. xschem, klayout, magic, are working, so I think docker-container was installed correctly. OS is Windows 11 and Docker desktop is v.4.17.1.

Hi, I am trying to run OpenROAD-flow-scripts in a native Ubuntu 22.04, but am continuously encountering the following error, any idea how to fix this? I have downloaded yosys and klayout as well as openroad and all of them are building and working fine. But when I try to make the flow script Makefile, I am encountering this particular error. I tried to change paths for yosys, but its still persistent.

Can someone help me with the LVS code error? My config file and error description files: [STEP 42] [INFO]: Running LVS (log: ../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/logs/signoff/42-lvs.lef.log)... [ERROR]: There are LVS errors in the design: See '../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/reports/signoff/42-neuron_core_dffram.lvs.rpt' for a summary and '../home/edabk/efabless_ver2/caravel_user_project/openlane/neuron_core_dffram/runs/23_12_08_14_46/logs/signoff/42-lvs.lef.log' for details. [ERROR]: Step 42 (lvs) failed with error: -code 1 -level 0 -errorcode NONE -errorinfo { while executing "throw_error" (procedure "quit_on_lvs_error" line 13) invoked from within "quit_on_lvs_error -rpt $count_lvs_rpt -log $log" (procedure "run_lvs" line 76) invoked from within "run_lvs" (procedure "run_lvs_step" line 10) invoked from within "run_lvs_step"} -errorline 1

Hey everyone, so I would like to dive into the transistor mismatch analysis for this PDK. From this classical paper on transistor mismatch (https://ieeexplore.ieee.org/document/572629), there are two major contributors to mismatch, one is due to

Vt

and another is due to the charge mobility (electrons

\mu_n

and holes

\mu_p

), and their mismatch equation is attached as the picture. In short, where could I find that parameter

Ap

for

Vt

and

\mu

? I know there is this slope file here: https://github.com/google/skywater-pdk-libs-sky130_fd_pr/blob/f62031a1be9aefe902d6[…]/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice But I am not 100% sure if they are really what I am looking for. For example, for the

Vt

there are two different slope values; and I do not see any ones related to the charge mobility. Any idea on this? Thanks.

Please help me solve these errors in cadence, i tried to import to cadence virtuoso GDSII file from sonnet software using XStream and got this message: Loading PDK Param Table '/usr/local/IC614/tsmc13/tsmc13rf/../skill/pdkParamTable.ile' INFO (XSTRM-217): Reading the layer map file, /usr/local/IC614/tsmc13/tsmc13rf/tsmc13rf.layermap WARNING (XSTRM-75): Target library 'project_hend' is attached to the technology library 'tsmc13rf'. Therefore, the technology file is opened in read-only mode. All the undefined layer-purpose pairs will be dropped. WARNING (XSTRM-107): Existing cells in the target library may be overwritten if the cell name in the Stream file is same as the cell name in the target library. Specify the Do Not Overwrite Existing Cells option and try again. INFO (XSTRM-163): You have not used the viaMap option. If a viaMap file, corresponding techfile or technology library exist, then use the -viaMap option for creating oaVia instances in the Streamed-In library. Using the -viaMap option improves performance and VM usage of applications using the Streamed-In design. For details on the viaMap option, refer to the "Design Data Translator's Reference" guide for XStream. INFO (XSTRM-220): 1. Translating STRUCTURE hend_lay_test_1 as cellView project_hend/hend_lay_test_1/layout WARNING (XSTRM-36): The objects in the stream layer-datatype '2:0' are ignored. This is because the stream layer-datatype pair is not specified in the layer map file. Specify the stream layer-datatype pair in the layer map file and try again.

Hi all, Any ideas to solve my hold violation problem?

Antenna Summary:
Source: /project/openlane/user_proj_example/runs/user_proj_example/reports/routing/41-antenna.rpt
Number of pins violated: 25
Number of nets violated: 25
[INFO]: check full report here: /project/openlane/user_proj_example/runs/user_proj_example/reports/final_summary_report.csv
[INFO]: There are no max slew violations in the design at the typical corner.
[ERROR]: There are hold violations in the design at the typical corner. Please refer to /project/openlane/user_proj_example/runs/user_proj_example/reports/routing/26-spef_extraction_sta.min.rpt.
[INFO]: Calculating Runtime From the Start...
[INFO]: flow failed for user_proj_example/2021.10.31_13.43.15 in 0h27m31s
[INFO]: Generating Final Summary Report...
[INFO]: Design Name: user_proj_example
Run Directory: /project/openlane/user_proj_example/runs/user_proj_example