What is the exact meaning of "Result: The top level cell failed pin matching." for netgen? I have two netlists with matching components and number of nodes and it is giving that error. I seem to remember a more explicit error if the connectivity in the netlist is different.

I'm currently testing the OSU FreePDK 45nm with the simple test design 'spm'. I'm encountering large no. of errors during the SPICE export and DRC check steps of the flow inspite of getting 0 violations after routing. Any idea what could be the cause of the error? I have attached the config.tcl, magic_spice.log and magic_drc.log for your reference. Kindly look into it.

greetings! How can i configure the sky130 pdk in the klayout for layout design of the simulated circuit from the xschem? any resources

does the linter also checks for verilog files included in the blackbox? We have openram memories that have delay and hold timing constructs. Verilator is complaining:

[ERROR]: Timing constructs found in the RTL. Please remove them or wrap them around an ifdef. It heavily unrecommended to rely on timing constructs for synthesis.
[ERROR]: Step 0 (verilator_lint_check) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "run_verilator" line 50)
    invoked from within
"run_verilator"
    (procedure "run_verilator_step" line 3)
    invoked from within
"run_verilator_step"} -errorline 1

Hello everyone, I was trying to analyze the corner impact on the circuit and I need to plot transient waveforms in different corners. I would appreciate it if anyone let me know how should I do that in xschem. Also, where can I find the script for plotting ngspice signals in matlab? Thanks @Tim Edwards

Hmm... in various points throughout my build I've gotten the following warnings at the end: • There are max slew violations in the design at the typical corner • There are max capacitance violations in the design at the typical corner • There are max fanout violations in the design at the typical corner What would be a good way to address each of these issues? More specifically, what knobs should I be adjusting in the configuration file for each warning?

Stefano: OpenSTA can do power analysis

Hi all! I am not able to access and install SKY130 pdk in #C01DH7SPX41 Did anyone else face this issue and could solve it? Thanks

Have anyone had any luck in installing openvaf in Windows? I downloaded MSVC build tools and installed it. But I cannot seem to do anything with the downloaded openvaf_23_5_0_windows_amd64 file (Note the no extension). Should I rename it to openvaf and add .exe? Or somehow build it using build tools? Help will be greatly appreciated

Hello. I'm using xschem with gf180mcu PDK. There are many digital stdcells I can use in xschem with SKY130 PDK. But I couldn't find them in xschem with gf180mcu PDK. Should I manually design latches, flip-flops, etc. to use them? or is there any sources that I can use in xschem? Thank you for reading my question.