Hey everyone, so I would like to dive into the transistor mismatch analysis for this PDK. From this classical paper on transistor mismatch (https://ieeexplore.ieee.org/document/572629), there are two major contributors to mismatch, one is due to

Vt

and another is due to the charge mobility (electrons

\mu_n

and holes

\mu_p

), and their mismatch equation is attached as the picture. In short, where could I find that parameter

Ap

for

Vt

and

\mu

? I know there is this slope file here: https://github.com/google/skywater-pdk-libs-sky130_fd_pr/blob/f62031a1be9aefe902d6[…]/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice But I am not 100% sure if they are really what I am looking for. For example, for the

Vt

there are two different slope values; and I do not see any ones related to the charge mobility. Any idea on this? Thanks.

Hello everyone, I was trying to analyze the corner impact on the circuit and I need to plot transient waveforms in different corners. I would appreciate it if anyone let me know how should I do that in xschem. Also, where can I find the script for plotting ngspice signals in matlab? Thanks @Tim Edwards

Hi, I'm trying to generate a custom openram macro for sky130, and I'm getting the familiar

ERROR: file design.py: line 46: Custom cell pin names do not match spice file:

error. The issues and chat history I've searched referencing this indicate the skywater pdk is not installed correctly, however, I ran

make install

, it looked successful, and I have the following files

ls technology/sky130/gds_lib/
sky130_sram_1kbyte_1rw1r_32x256_8.gds  sky130_sram_2kbyte_1rw1r_32x512_8.gds
sky130_sram_1kbyte_1rw1r_8x1024_8.gds  sram_1rw1r_32_256_8_sky130.gds

Hi! Can someone please help me with the following?

I'm currently testing the OSU FreePDK 45nm with the simple test design 'spm'. I'm encountering large no. of errors during the SPICE export and DRC check steps of the flow inspite of getting 0 violations after routing. Any idea what could be the cause of the error? I have attached the config.tcl, magic_spice.log and magic_drc.log for your reference. Kindly look into it.

Hello, When trying to get the back annotation feature working. I have in place:

* Is this option needed, this option causes the ngspice error:
* "Warning from checkvalid: vector @m.xm1.msky130_fd_pr__pfet_01v8[ib] is not available or has zero length."
* .option savecurrents
.save all

When the

.option savecurrents

is specified, this causes no new RAW file to be created, but an error to occur, is this usage error or a bug ? When I attempt to "load waves" with code.sym "xschem raw_read $netlist_dir/testbench.raw tran" no error is shown, no indication an action was performed occurs and no update to visual seen. When I use the menu "Graphs -> Annotate Operating Point ... -> pick RAW file -> OK" the visual updates with question marks "? ?" the only data that is updated are the ammeter.sym and spice_probe.sym I added to the design. None of the transistors show values. I think I need to inject a wave graph into the schematic view, to provide an X axis time reference to show sample for, can''t see an obvious design/*.sym to insert for this, so hunting for a project with that configured. Also what is the best symbol to be using to inject test points for data collection (I and V for example), ideally with a quick toggle button list to disable/enable (without need to rework the schematic, to remove the injected symbol when you want to disable it). This would then modify the netlist creation and ngspice config accordingly to the disable/enable state of the individual test point. Also after some time in usage of xschem the application refuses to take any more mouse click input to select items in the main design area. Menu items work ok, a restart always fixes it. Is this is known matter maybe with Tk/X11, using Linux/Xwayland ? Thanks

Hello I a new to openlane and have been trying to install it for a while, after cloning the repo and after I cd into the openlane2 directory i execute the nix-shell which builds to about 90% and then throws a build error, for context i am using Ubuntu in WSL.

Hello, all. During LVS, there is an error as below. How can I solve this problem? RuntimeError: Can't find a schematic counterpart for the top cell current_cell_1X - use 'same_circuit' to establish a correspondence in Executable

Could anyone give some advice about caravel on IIC-OSIC-TOOLS (docker-container)? I've been using IIC-OSIC TOOLS (non-docker version) and it works well. Now I'm trying docker-version of IIC-OSIC-TOOLS, but I'm stuck at setup. When I try the flow of caravel_user_project, 'make setup' fails with errors below. % cd caravel_user_project % mkdir dependencies % export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src % export PDK_ROOT=$(pwd)/dependencies/pdks % export PDK=sky130B % make test (snip) make[2]: Entering directory '/foss/designs/caravel_user_project/dependencies/openlane_src' Makefile23 warning: undefined variable 'DOCKER_SWAP' Makefile26 warning: undefined variable 'DOCKER_MEMORY' Makefile42 warning: undefined variable 'ROUTING_CORES' /bin/sh: 1: docker: Permission denied make[2]: * [Makefile114 pull-openlane] Error 127 make[2]: Leaving directory '/foss/designs/caravel_user_project/dependencies/openlane_src' make[1]: * [Makefile84 openlane] Error 2 make[1]: Leaving directory '/foss/designs/caravel_user_project/openlane' make: * [Makefile181 openlane] Error 2 I also tried without changing environmental variables (means, OPENLANE_ROOT=/foss/tools/openlane and PDK_TOOR=/foss/pdks), but 'make setup' also stopped due to permission errors in openlane. Other tools, e.g. xschem, klayout, magic, are working, so I think docker-container was installed correctly. OS is Windows 11 and Docker desktop is v.4.17.1.

Is there a way to convert a Verilog netlist to SPICE netlist to perform a mixed-signal simulation on a gate level with analog circuitry?