We are getting the error There are unmapped cells after synthesis. We tried every placement strategy. Is there something we can do to fix that?

Hi, i saw some post on gm/Id method, an IEEE paper for the same https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=535416&tag=1 However, to plot graphs, 1. gm/Id Vs Vgs --> for gate Voltage 2. gm/Id Vs Vdsat --> i.e. VDD (also called as gate overdrive voltage) 3. gm/Id Vs gm/gds --> intresic gain 4. gm/Id Vs Vth ---> threshold voltage 5. gm/Id Vs Id/W ---> Current Density i'm searching for ngspice commands to be used with sky130, from some time. But, with few forms not able to find help. So, can anyone having example for such. It would be great help.

Hello, This is related to the IP hardening process. From the tutorials on efabless.com, I understand that IP hardening is 2-step process (1: Harden your design, 2: Instantiate the netlist within user_project_wrapper and then harden the complete wrapper). Can we simply instantiate our custom RTL in user_project_wrapper and harden only once?

Hey everyone, I'm trying to netlist a sky130 xschem schematic using the xschem CLI, but everytime it give me the following error. Does anyone know how to fix this? global_spice_netlist(): problems opening netlist file

Hello, I am experiencing an issue regarding an LVS for an encoder using standard cells. I appears as though, from the immediate lvs report, that there are two extra instances of an nfet and pfet in my circuit 2(Mag spice, or the longer file). However, looking at the spice file for circuit 2, there are no fet instances when looking at the top level subcircuit. I do not know if this issue is because of the use of standard cells and I am missing something, or something else entirely.

Please help me solve these errors in cadence, i tried to import to cadence virtuoso GDSII file from sonnet software using XStream and got this message: Loading PDK Param Table '/usr/local/IC614/tsmc13/tsmc13rf/../skill/pdkParamTable.ile' INFO (XSTRM-217): Reading the layer map file, /usr/local/IC614/tsmc13/tsmc13rf/tsmc13rf.layermap WARNING (XSTRM-75): Target library 'project_hend' is attached to the technology library 'tsmc13rf'. Therefore, the technology file is opened in read-only mode. All the undefined layer-purpose pairs will be dropped. WARNING (XSTRM-107): Existing cells in the target library may be overwritten if the cell name in the Stream file is same as the cell name in the target library. Specify the Do Not Overwrite Existing Cells option and try again. INFO (XSTRM-163): You have not used the viaMap option. If a viaMap file, corresponding techfile or technology library exist, then use the -viaMap option for creating oaVia instances in the Streamed-In library. Using the -viaMap option improves performance and VM usage of applications using the Streamed-In design. For details on the viaMap option, refer to the "Design Data Translator's Reference" guide for XStream. INFO (XSTRM-220): 1. Translating STRUCTURE hend_lay_test_1 as cellView project_hend/hend_lay_test_1/layout WARNING (XSTRM-36): The objects in the stream layer-datatype '2:0' are ignored. This is because the stream layer-datatype pair is not specified in the layer map file. Specify the stream layer-datatype pair in the layer map file and try again.

Hello, I'm having error with the following line: ".include ~/skywater-pdk-libs-sky130_fd_pr/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.corner.spice". It returns error of: "Error in line include "sky130_fd_pr__esd_nfet_05v0_nvt.pm3" Not enough parameters"

if I want to do gate level simulations with designs that include openram, is there a gatelevel verilog version of openram? I assume not, but I don't know how to proceed without one

Following the success of the openEMS simulations, I'm now looking to improve the BEOL model, and I'm looking at the silicon substrate now... Taking a look into the semiconductor criteria subsection at https://skywater-pdk.readthedocs.io/en/main/rules/assumptions.html#process-stack-diagram There's no indication of the P wafer dopant concentration or resistivity, and that's a vital piece of information for simulating inductors and other structures that "see" the naked substrate. I'm taking the substrate information of IHP process (2 S/m for the wafer, 5 S/m for a thin epitaxial P layer), but I'd like to ask: 1) is there a value for the wafer resistivity/conductivity for sky130? 2) does the sky130 feature an epitaxial layer, and if yes, what is its resistivity/conductivity?

Hello all, Recently, I simulated a Track and hold circuit in Xschem+NGspice and exported the simulation raw file for post processing fft. The signal in time domain seems to be perfect but in frequency domain it looks like something is wrong, if anyone can help, I'd be very thankful. attached the circuit + post processing script + output wave form in time and frequency domains.

clear all;
close all;
clc;
path = "D:\studies\SHA.raw";
[signals, signals_values] = parse_tran_ngspice(path);
time = signals_values(find(strcmp(signals, "time")),:);
y = signals_values(find(strcmp(signals, "v(hold)")),:);
plot(time,y);
N = length(y);
s = abs(fft(y,N))
%s=s(1:N/2);
f= (0:length(s)-1)/N;
sdb = 20*log10(s);
plot(f, sdb);
xlabel('Frequency [ f / f_s ]');
ylabel('Amplitude [ dBFS ]');