What layer do I need to make a proper tap for pmos devices in magic? I have imported a design from Cadence Layout XL, but device taps that pass those DRCs have layers are not clean in magic checks. For example, placing pdiff to fix N-tap overlap of N-tap contact < 0.12um (licon.7) results in a "Can't overlap those layers" error. Other commenters have mentioned a "psd" layer, but for some reason I don't have that naming convention, only pdiffusion. A number of other layers have similarly strange names.

Hello all, Recently, I simulated a Track and hold circuit in Xschem+NGspice and exported the simulation raw file for post processing fft. The signal in time domain seems to be perfect but in frequency domain it looks like something is wrong, if anyone can help, I'd be very thankful. attached the circuit + post processing script + output wave form in time and frequency domains.

clear all;
close all;
clc;
path = "D:\studies\SHA.raw";
[signals, signals_values] = parse_tran_ngspice(path);
time = signals_values(find(strcmp(signals, "time")),:);
y = signals_values(find(strcmp(signals, "v(hold)")),:);
plot(time,y);
N = length(y);
s = abs(fft(y,N))
%s=s(1:N/2);
f= (0:length(s)-1)/N;
sdb = 20*log10(s);
plot(f, sdb);
xlabel('Frequency [ f / f_s ]');
ylabel('Amplitude [ dBFS ]');

Hi, I face issue while saving already existing schematic in xschem. It says: File opening for write failed! save_schematic(): problems opening file /home/srini/Desktop/ngspice-ngspice/sky130_example/test.sch I made changes in the circuit but unable to save it? I am unable to create any new file as well.

Can someone help. I am facing LVS mismatch issue when I run user_project_wrapper.v but when I run user_proj_example.v there's no issue of LVS. Thanks in advance.

Hi, I'm trying to find out what the parameters ng and m mean in the mos models of sky130. I believe they represent gate fingers and multipliers respectively, but I just can't be sure, and I can't find much info about it on the internet. Edit: Additionally, I would also like to know the upper/lower limits on these parameters, if possible. A source that directs me to those parameters works as well.

Following the success of the openEMS simulations, I'm now looking to improve the BEOL model, and I'm looking at the silicon substrate now... Taking a look into the semiconductor criteria subsection at https://skywater-pdk.readthedocs.io/en/main/rules/assumptions.html#process-stack-diagram There's no indication of the P wafer dopant concentration or resistivity, and that's a vital piece of information for simulating inductors and other structures that "see" the naked substrate. I'm taking the substrate information of IHP process (2 S/m for the wafer, 5 S/m for a thin epitaxial P layer), but I'd like to ask: 1) is there a value for the wafer resistivity/conductivity for sky130? 2) does the sky130 feature an epitaxial layer, and if yes, what is its resistivity/conductivity?

How to check temperature variation in xschem? I am designing BGR.

Has anyone tried using the keep synthesis attribute? Is following the correct way to apply it to a signal named e1: (* keep *) wire[14:0] e1; ? If the attribute is successfully getting applied by yosys, does the synthesis log reflect it anywhere?

お初の方もいらっしゃると思うので、自作ツールの紹介をさせてください。 設定レジスタ (CSR) の RTL などを、レジスタマップから自動生成するツールを作っています。 https://github.com/rggen/rggen 対応するレジスタマップのフォーマットは以下の通りです。 • JSON • TOML • YAML • Ruby • Sifive DuH • スプレッドシート (MS Excel, Libreoffice Calc, CSV) これらのフォーマットで記述したレジスタマップから、以下のファイルを生成します。 • RTL (SV/Verilog/VHDL) ◦ APB/AXI4 Lite/Wishbone に対応 • UVM RAL model • C header file • Markdown 例えば、以下のレジスタマップから、 • https://github.com/rggen/rggen-sample/blob/master/block_0.ym • https://github.com/rggen/rggen-sample/blob/master/block_0.toml • https://github.com/rggen/rggen-sample/blob/master/block_0.rb • https://github.com/rggen/rggen-sample/blob/master/block_0.xlsx l 以下の生成物を、生成することができます。 • https://github.com/rggen/rggen-sample/blob/master/block_0.sv • https://github.com/rggen/rggen-sample/blob/master/block_0.v • https://github.com/rggen/rggen-sample/blob/master/block_0.vhd • https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv • https://github.com/rggen/rggen-sample/blob/master/block_0.h • https://github.com/rggen/rggen-sample/blob/master/block_0.md MIT ライセンスで公開している OSS なので、趣味商用問わず無償で利用可能です。 機会があれば、見てみてください。

Hello Everyone, I have built a counter in verilog which I want to integrate with my analog circuit at the schematic level in xschem and then perform spice simulations, how do I do that, in my view I have to somehow synthesize the verilog code into a spice file and then create a symbol out of that spice file to put it on the schematic window.