What layer do I need to make a proper tap for pmos devices in magic? I have imported a design from Cadence Layout XL, but device taps that pass those DRCs have layers are not clean in magic checks. For example, placing pdiff to fix N-tap overlap of N-tap contact < 0.12um (licon.7) results in a "Can't overlap those layers" error. Other commenters have mentioned a "psd" layer, but for some reason I don't have that naming convention, only pdiffusion. A number of other layers have similarly strange names.

Hi, I face issue while saving already existing schematic in xschem. It says: File opening for write failed! save_schematic(): problems opening file /home/srini/Desktop/ngspice-ngspice/sky130_example/test.sch I made changes in the circuit but unable to save it? I am unable to create any new file as well.

@Stefan Schippers I am trying to plot gm graphs for gm/Id simulation but I cannot see plots when I type the plot command in simulation block. I can see the plot when I run the command in ngspice window.

Hello, all. I'm facing latch-up error in DRC as below. but I dont' have any idea how to resolve it after reading descriptions. Could you give me any advice? Within 15um from the edge of the NCOMP connected to I/O pad (marked by Latchup_MK): Max Nwell tap distance to PCOMP inside Nwell (irrespective of its direct connection to Pad) = 2

Hello all, Recently, I simulated a Track and hold circuit in Xschem+NGspice and exported the simulation raw file for post processing fft. The signal in time domain seems to be perfect but in frequency domain it looks like something is wrong, if anyone can help, I'd be very thankful. attached the circuit + post processing script + output wave form in time and frequency domains.

clear all;
close all;
clc;
path = "D:\studies\SHA.raw";
[signals, signals_values] = parse_tran_ngspice(path);
time = signals_values(find(strcmp(signals, "time")),:);
y = signals_values(find(strcmp(signals, "v(hold)")),:);
plot(time,y);
N = length(y);
s = abs(fft(y,N))
%s=s(1:N/2);
f= (0:length(s)-1)/N;
sdb = 20*log10(s);
plot(f, sdb);
xlabel('Frequency [ f / f_s ]');
ylabel('Amplitude [ dBFS ]');

Duplicating this error message, because apparently the ngspice

plot

instruction cannot handle lines of a bus, although

display

can handle signals like

io_out[11]

just fine.

Following the success of the openEMS simulations, I'm now looking to improve the BEOL model, and I'm looking at the silicon substrate now... Taking a look into the semiconductor criteria subsection at https://skywater-pdk.readthedocs.io/en/main/rules/assumptions.html#process-stack-diagram There's no indication of the P wafer dopant concentration or resistivity, and that's a vital piece of information for simulating inductors and other structures that "see" the naked substrate. I'm taking the substrate information of IHP process (2 S/m for the wafer, 5 S/m for a thin epitaxial P layer), but I'd like to ask: 1) is there a value for the wafer resistivity/conductivity for sky130? 2) does the sky130 feature an epitaxial layer, and if yes, what is its resistivity/conductivity?

Hello Everyone, I have built a counter in verilog which I want to integrate with my analog circuit at the schematic level in xschem and then perform spice simulations, how do I do that, in my view I have to somehow synthesize the verilog code into a spice file and then create a symbol out of that spice file to put it on the schematic window.

Hey everyone, I'm trying to netlist a sky130 xschem schematic using the xschem CLI, but everytime it give me the following error. Does anyone know how to fix this? global_spice_netlist(): problems opening netlist file

In Xschem when using such a symbol (the 'nf' one) and then having

W=12 L=0.5 nf=3

The W is the total width right ? Or the per-finger one ? I was pretty sure it was the total one given you have stuff like

ad="'int((nf+1)/2) * W / nf * 0.29'"

in the param box ( the

W/nf

being the clue ).