Using IHP SG13G2 open PDK and klayout. Does anyone know how to get rid of this active filler area, density, global metal drc errors??? I've been trying different area and filling them but this ertror won't go. Slack Conversation

hi, now I'm getting this error in my project in open lane "[ERROR]: There are hold violations in the design at the typical corner", this error point me to a file with the timings. What I need to change to fix the hold violation error?, increment target density, bigger chip, etc ..

@Stefan Schippers I am trying to do a basic parametric sweep (snapshot attached). In the waveform graph, how to differentiate between the traces? i.e., how to show the parameter associated with every VOUT trace? Also for the cursors, how to jump from one VOUT trace to another? Is this explained in xschem manual? I couldn't find this.

Hello everyone, I've just integrated analog macro (OpAmp) into caravel (user_project_wrapper), providing GDS, LEF, SPICE (generated from xschem, copied to spi/lvs subdirectory), Verilog stub. Everything is fine while hardening user_project_wrapper (= flow is successfull, including LVS) and resulting GDS looks as expected. However, during precheck LVS is failing. According to "lvs.report", everything seems to be ok (screenshot included).

Cell pin lists are equivalent.

Device classes user_project_wrapper and user_project_wrapper are equivalent.

"lvs.log" states that:

circuit opamp_cascode contains no devices.

and there's a warning:

Warning: device level LVS may be incomplete due to 1 unflattened cell(s)

However, everything seems to be totally fine, because:

Circuits match uniquely.

On the other hand, "LVS_check.log" states that, for analog macro:

Circuit 1 contains 98 devices, Circuit 2 contains 98 devices.

Circuit 1 contains 4605 nets,    Circuit 2 contains 6017 nets. *** MISMATCH ***

Final result:

Top level cell failed pin matching.

In "soft.report", I see some mismatches (example screenshot included).

Hi, I face issue while saving already existing schematic in xschem. It says: File opening for write failed! save_schematic(): problems opening file /home/srini/Desktop/ngspice-ngspice/sky130_example/test.sch I made changes in the circuit but unable to save it? I am unable to create any new file as well.

Has anyone else run into the problem of missing the “Import SPICE” option under the “File” dropdown menu? I am running Magic 8.3.485 on a Mac M1 and everything appears to have compiled fine, however I’m missing this command. See two screenshots below, one showing a screenshot of a video tutorial, and the other from my local machine:

Hi everyone, I tried to use the OpenRAM memory compiler to generate a 32x512 memory but run into some problems. The error messages said:

Technology: sky130
Total size: 8192 bits
Word size: 32
Words: 256
Banks: 1
Write size: None
RW ports: 1
R-only ports: 0
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
Only generating nominal corner timing.
ERROR: file sram_config.py: line 132: Invalid number of cols including rbl(s): 129. Total cols must be divisible by 2

I don't know how to interpret this error because I don't know where this 129 is coming from. Has anyone run into this problem before?

@Stefan Schippers I am trying to plot gm graphs for gm/Id simulation but I cannot see plots when I type the plot command in simulation block. I can see the plot when I run the command in ngspice window.

I'm trying to extract spice from a GDS file (Tiny Tapeout ROM) and simulate it in NG Spice to dump the ROM contents. This is how I'm extracting the spice: https://github.com/TinyTapeout/tt06-rom-spice-sim/blob/master/extract_spice.sh

Hello Everyone, I have built a counter in verilog which I want to integrate with my analog circuit at the schematic level in xschem and then perform spice simulations, how do I do that, in my view I have to somehow synthesize the verilog code into a spice file and then create a symbol out of that spice file to put it on the schematic window.