Hey! Seems like there is bug in xschem (or ngspice) using sky130 pdk: If doing a noise simulation (.noise) within placed a nfet_01v8 in xschem and saving data in ngspice using write noiseSim.raw (for example), ngspice crashes and writes an error: "vector @m.xm1.msky130_fd_pr___nfet_01v8[ib] is not available or has zero length. free(): invalid pointer ...". It seems that only nfet01v[id] has data and ngspice can't handle that. A temporary solution would be (for example) instead of write noiseSim.raw: setplot noise1 write noiseSim.raw @m.xm1.msky130_fd_pr__nfet_01v8[id] @r1[i] inoise_spectrum onoise_spectrum set appendwrite setplot noise2 write noiseSim.raw @m.xm1.msky130_fd_pr__nfet_01v8[id] @r1[i] inoise_total onoise_total

Duplicating this error message, because apparently the ngspice

plot

instruction cannot handle lines of a bus, although

display

can handle signals like

io_out[11]

just fine.

Hey everyone, I'm trying to netlist a sky130 xschem schematic using the xschem CLI, but everytime it give me the following error. Does anyone know how to fix this? global_spice_netlist(): problems opening netlist file

How to check temperature variation in xschem? I am designing BGR.

Can someone help. I am facing LVS mismatch issue when I run user_project_wrapper.v but when I run user_proj_example.v there's no issue of LVS. Thanks in advance.

Using IHP SG13G2 open PDK and klayout. Does anyone know how to get rid of this active filler area, density, global metal drc errors??? I've been trying different area and filling them but this ertror won't go. Slack Conversation

greetings! How can i configure the sky130 pdk in the klayout for layout design of the simulated circuit from the xschem? any resources

Hi all, I'm tring to do post synthesis simulation using results produced by openlane flow. I encountered following warnings and results are not matching with pre-synthesis, I used following commands to execute.Is there any alternative method to do gate level simulation? Please help me figure this.

iverilog fsm_adder.v adder_fsm_tb.v sky130_sram_1kbyte_1rw1r_32x256_8.v sky130_fd_sc_hd.v primitives.v

vvp a.out

gtkwave dump.vcd

お初の方もいらっしゃると思うので、自作ツールの紹介をさせてください。 設定レジスタ (CSR) の RTL などを、レジスタマップから自動生成するツールを作っています。 https://github.com/rggen/rggen 対応するレジスタマップのフォーマットは以下の通りです。 • JSON • TOML • YAML • Ruby • Sifive DuH • スプレッドシート (MS Excel, Libreoffice Calc, CSV) これらのフォーマットで記述したレジスタマップから、以下のファイルを生成します。 • RTL (SV/Verilog/VHDL) ◦ APB/AXI4 Lite/Wishbone に対応 • UVM RAL model • C header file • Markdown 例えば、以下のレジスタマップから、 • https://github.com/rggen/rggen-sample/blob/master/block_0.ym • https://github.com/rggen/rggen-sample/blob/master/block_0.toml • https://github.com/rggen/rggen-sample/blob/master/block_0.rb • https://github.com/rggen/rggen-sample/blob/master/block_0.xlsx l 以下の生成物を、生成することができます。 • https://github.com/rggen/rggen-sample/blob/master/block_0.sv • https://github.com/rggen/rggen-sample/blob/master/block_0.v • https://github.com/rggen/rggen-sample/blob/master/block_0.vhd • https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv • https://github.com/rggen/rggen-sample/blob/master/block_0.h • https://github.com/rggen/rggen-sample/blob/master/block_0.md MIT ライセンスで公開している OSS なので、趣味商用問わず無償で利用可能です。 機会があれば、見てみてください。

Has anyone tried using the keep synthesis attribute? Is following the correct way to apply it to a signal named e1: (* keep *) wire[14:0] e1; ? If the attribute is successfully getting applied by yosys, does the synthesis log reflect it anywhere?