Hi all, I'm tring to do post synthesis simulation using results produced by openlane flow. I encountered following warnings and results are not matching with pre-synthesis, I used following commands to execute.Is there any alternative method to do gate level simulation? Please help me figure this.

iverilog fsm_adder.v adder_fsm_tb.v sky130_sram_1kbyte_1rw1r_32x256_8.v sky130_fd_sc_hd.v primitives.v

vvp a.out

gtkwave dump.vcd

Hey everyone, I'm trying to netlist a sky130 xschem schematic using the xschem CLI, but everytime it give me the following error. Does anyone know how to fix this? global_spice_netlist(): problems opening netlist file

I'm trying to extract spice from a GDS file (Tiny Tapeout ROM) and simulate it in NG Spice to dump the ROM contents. This is how I'm extracting the spice: https://github.com/TinyTapeout/tt06-rom-spice-sim/blob/master/extract_spice.sh

Hello. I tried to put macros into my project. I have finished placing the macros and setting up the config.json. I proceed to run openlane for synthesis and tapeout. I get a Running Global Routing error code. Specifically, the error: [ERROR GRT-0119] Routing congestion too high. Check the congestion heatmap in the GUI and load /home/edabk/efabless/caravel_user_project/openlane/neuron_core_dffram/runs/23_11_28_11_46/tmp/routing/groute-congestion.rpt in the DRC viewer.

Hi all, I am new using open source EDA tools. Is there any way of converting a .lib.json into a .lib? I am trying to perform synthesis with Yosys using sky130 PDK, however I noticed there is only .lib.json available in the official GitHub repository.

In Xschem when using such a symbol (the 'nf' one) and then having

W=12 L=0.5 nf=3

The W is the total width right ? Or the per-finger one ? I was pretty sure it was the total one given you have stuff like

ad="'int((nf+1)/2) * W / nf * 0.29'"

in the param box ( the

W/nf

being the clue ).

Hi everyone, I'm stuck on routing congestion for our final user_project_wrapper build. I really can't understand the way in which the router is behaving. The ports its having trouble with appear to be just those along the bottom edge of the macro. I've brought these right out to the edge, and they are few and far between (only about 60 ports spanning a 1200um edge) but its still having trouble with congestion. It seems to be sending all the wires up a narrow corridor to the left of the macro, and then across and down, why? There's loads of empty space below it!

Hey, I am trying to set up Cadence EMX with the Sky130 Cadence PDK; has anyone made the .proc file with the process stack information used for setting up EMX?

@Tim Edwards We are looking into implementing some inductors in Skywater 130 and I am not sure where we could get some references. Are there any primitives? can I find them in open_pdks or generate them using Magic? @Chirag Agarwal FYI

Hello, all. I'm facing latch-up error in DRC as below. but I dont' have any idea how to resolve it after reading descriptions. Could you give me any advice? Within 15um from the edge of the NCOMP connected to I/O pad (marked by Latchup_MK): Max Nwell tap distance to PCOMP inside Nwell (irrespective of its direct connection to Pad) = 2