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Hi everyone, I tried to use the OpenRAM memory compiler to generate a 32x512 memory but run into som...
# openram
p
Hi everyone, I tried to use the OpenRAM memory compiler to generate a 32x512 memory but run into some problems. The error messages said:
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Technology: sky130
Total size: 8192 bits
Word size: 32
Words: 256
Banks: 1
Write size: None
RW ports: 1
R-only ports: 0
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
Only generating nominal corner timing.
ERROR: file sram_config.py: line 132: Invalid number of cols including rbl(s): 129. Total cols must be divisible by 2
I don't know how to interpret this error because I don't know where this 129 is coming from. Has anyone run into this problem before?
Some context: 1. I cloned the repo from the 
stable
branch here 2. I sourced the 
setpaths.csh
3. I set the 
PDK_ROOT
to the skywater 130 PDKs 4. I run 
make install
in the OpenRAM repo, but it gave me an error saying that it can't find the 
sky130_fd_bd_sram
folder. 5. I manually cloned the repo from here, and renamed it to 
sky130_fd_bd_sram
6. I do 
make install
again, and this time it succeed 7. I prepared the 
config.py
, within it I set the SRAM size to be 32x256, and use sky130 technology 8. Then I ran the tool, and were stuck by this divisible-by-2 error
m
The single port bitcell has lithography restrictions that require an even number of rows and columns. Right now, OpenRAM uses a replica column and dummy row for timing so there needs to be an extra row and column added to make it even. You can do this with num_spare_cols and num_spare_rows. Take a look at the examples in the dev branch of https://github.com/efabless/sky130_sram_macros/tree/dev
We are updating to resolve the PDK issue. You may want to use dev rather than the stable branch
p
Thank you Prof. Guthaus! I switched to the 
dev
branch and set both 
num_spare_cols
and 
num_spare_rows
to be 1. The divisible-by-2 error goes away! However, I ran into another error:
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Traceback (most recent call last):
  File "/somelongpath/OpenRAM/compiler/base/utils.py", line 110, in get_gds_size
    return _GDS_SIZE_CACHE[k]
KeyError: ('sky130_fd_bd_sram__sram_sp_wlstrapa_p', '/somelongpath/OpenRAM/technology/sky130/gds_lib/sky130_fd_bd_sram__sram_sp_wlstrapa_p.gds', (0.001, 1e-09), (81, 2))
When I switched to the dev-branch, I did 
make pdk
and 
make install
again. Is there anything else I should do?
m
I've never seen that error... Hmm.
It's having a problem reading the cells for the array though.
p
I am using a very old version of google skywater pdk that is installed on our machine a year ago, could it be the problem?
originally I thought it will not be a problem, because I thought 
make pdk
will help me update the pdk to the latest version. But I checked my PDK_ROOT it still points to my old pdk
m
Oh, yes. There were updates
If something exists, my Makefile won't get a newer version
p
I see, I will check on that. Thanks!
a
I wonder where do we get this cell? It’s not in the 
skywater-pdk-libs-sky130_fd_bd_sram
repo, so it does not seem to be copied into technology/sky130/
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elif version == "wlstrapa_p":
            self.name = "sky130_fd_bd_sram__sram_sp_wlstrapa_p"
p
^ same question here if you look at the SRAM folder, you will not see this 
sram_sp_wlstrapa_p
cell
if you hack this file 
/OpenRAM/technology/sky130/modules/sky130_internal.py
, and force it to use 
sram_sp_wlstrapa
instead of 
sram_sp_wlstrapa_p
, then it will compile. However I don't think I am allowed to do this hacky step...
m
This was missing in the PDK but we added it recently. The single port macros are still in dev and haven't been tested in silicon yet (waiting for mpw2). This repo may be more up to date until we push charges to the other repos: https://github.com/VLSIDA/sky130_fd_bd_sram
Changing the reference will NOT work properly
a
Ah I see. Maybe we can temporarily change the git repo link in the dev Makefile to https://github.com/VLSIDA/sky130_fd_bd_sram
m
I've done that locally but don't want to commit that to dev...
We may forget to switch it back
👍 1
p
I found that this problem only exists in single-port sram when I switched to use 1rw1r SRAM it worked
m
Yes, that is a single port cell
sram_sp -> single port
p
I see, we will use the dual-port one for now. After the single port cell is tested in silicon we may want to switch back to use single port, will follow up on this and look forward to the good news! Thanks!
m
Yes, that is what I would recommend for now. There are a few things that could be issues on the single port.
👌 1
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