Hi everyone, I tried to use the OpenRAM memory compiler to generate a 32x512 memory but run into some problems. The error messages said:

Technology: sky130
Total size: 8192 bits
Word size: 32
Words: 256
Banks: 1
Write size: None
RW ports: 1
R-only ports: 0
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
Only generating nominal corner timing.
ERROR: file sram_config.py: line 132: Invalid number of cols including rbl(s): 129. Total cols must be divisible by 2

I don't know how to interpret this error because I don't know where this 129 is coming from. Has anyone run into this problem before?

Has anyone simulated transient noise in SW130? If so, how did the models behave? Were the sims accurate? Just about to start running transient noise so any info would be most appreciated. Txs

Warning: PDK_ROOT env. var. not found or empty, trying to find an open_pdks install No open_pdks installation found, set PDK_ROOT env. var. and restart xschem setup_tcp_bespice: success : listening to TCP port: 2022

We are getting the error There are unmapped cells after synthesis. We tried every placement strategy. Is there something we can do to fix that?

Has anyone else run into the problem of missing the “Import SPICE” option under the “File” dropdown menu? I am running Magic 8.3.485 on a Mac M1 and everything appears to have compiled fine, however I’m missing this command. See two screenshots below, one showing a screenshot of a video tutorial, and the other from my local machine:

Hi, does anyone know if there is a transmission gate cell in HV standard cells? Thanks

Hi, I am facing issue while running yosys synthesis with latest openroad flow scripts for my ethernet design. Error shown below: 41. Executing TECHMAP pass (map to technology primitives). 41.1. Executing Verilog-2005 frontend: ./platforms/asap7/yoSys/cells_latch.v 41.2. Continuing TECHMAP pass. 42. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). 42.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). ERROR: FF eth_top.$auto$simplemap.cc:527:simplemap_adff_sdff$26021 (type $_DFF_PP0_) cannot be legalized: dffs with async set or reset are not supported Command exited with non-zero status 1 Any suggestion how to fix it?

Duplicating this error message, because apparently the ngspice

plot

instruction cannot handle lines of a bus, although

display

can handle signals like

io_out[11]

just fine.

Is there any tutorial for klayout and ihp-sg13g2? I would like to make a simple circuit, such as an inverter, extract a netlist and run it. I can already run netlists in ngspice using the openVAF models. I just need to learn the layout part now.

@Stefan Schippers I am trying to plot gm graphs for gm/Id simulation but I cannot see plots when I type the plot command in simulation block. I can see the plot when I run the command in ngspice window.