Hi @Tim Edwards, After solving the two problems that you helped me with in the other threads, now I wanted to apply that in a ring oscillator, to obtain the LVS, but I have a problem, although the devices match me, I have a problem with the pins, unlike the another one that was an internal cell, here in xschem I disabled the LVS netlist, but the design in mag if I flattened it as you mentioned, do you still know what the problem could be?

@Juan Andres Looks like

inverter_blo.spice

and

inverter_blo_mag.spice

are the same file. Anyways, you need to add some pin/text layers to the top level layout.

It's true I'm sorry

There are pin layers and text layers. I’m not sure what the tech file recognizes as pins with your version of the pdk. Take a look at the inverter layout that passed LVS and see what layer the pins/text are on.

How can I look at that?

Is there a pin layer? You might need a text layer and a rectangular pin layer for ports.