Hi, I have some issues with extraction of parasites and the end I have only capacitance parasites no resistance

You have hierarchy in your design. The immediate error is that you don't have

.sim

files for all the subcells. However, I would not trust the full R-C extraction result on a hierarchical layout because there are just too many problems dealing with subcell overlaps. I recommend just flattening the design and running the R-C extraction on the flattened design. Assuming that

inverter_blo

is your top level, then start with:

load inverter_blo
select top cell
expand
flatten inverter_blo_flat
load inverter_blo_flat
cellname delete inverter_blo
cellname rename inverter_blo_flat inverter_blo
select top cell

Do not save the resulting flattened cell; use it only for the full R-C extraction and then quit without saving.

Hi @Tim Edwards, I did the extraction R and C but I have this error when I run the file inverter_blo.spice My command are: Extract do local Extract all Ext2sim labels on Ext2sim Extresist tolerance 10 Extresist Ext2spice lvs Ext2spice crhresh 0 Ext2spice exteresist on Ext2spice

The posted

inverter.spice

file is not from a flattened netlist.

I don’t understand

Well, I don't quite understand either. In your screenshot from a few hours ago, you were extracting the layout cell

inverter_blo

. I told you how to flatten it before running extresist. The resulting netlist should be called

inverter_blo.spice

and it should not contain any subcircuits other than itself. However, your

inverter_blo.spice

that you posted above is a simulation testbench. So maybe it is cell

inverter

and not

inverter_blo

that you want to be flattening and running extraction on?

oh ok, in that screenshot it was the top, so what I did was take the inside of the inverter, which is called an inverter, so I did the whole process to this same block and it didn't give me an error, it creates the paraist resistors and capacitances, Now I want to simulate that block for a post latout, but it gives an error, but apparently it comes from magic

You should not have subcircuits in your final netlist

inverter.spice

if you did: (Note: corrected typo; it's "extresist tolerance 10", not "extresist threshold 10".)

load inverter
select top cell
expand
flatten inverter_flat
load inverter_flat
cellname delete inverter
cellname rename inverter_flat inverter
select top cell
extract all
ext2sim labels on
ext2sim
extresist tolerance 10
extresist
ext2spice lvs
ext2spice cthresh 0
ext2spice extresist on
ext2spice

But if I have several inverters, like a ring oscillator that has several sub circuits, can't it be there then?

Is there any tutorial for RC extraction? I thought extresist didn't work with ext2spice

@Luis Henrique Rodovalho: There is an extresist tutorial here: http://opencircuitdesign.com/magic/tutorials/tut8.html but I have no idea how relevant it is currently. extresist has worked with ext2spice but in varying degrees of success over the course of my spotty efforts to update it to match the rest of magic. There are still a few issues here and there (most of which are related to hierarchy; thus the advice to flatten a circuit first), but I have been getting valid netlists out of it.

@Tim 'mithro' Ansell, I have this error % extresist threshold 10 Unknown option: threshold

Sorry, it's "tolerance", not "threshold". I'll correct my post above.

i have this error % extresist Port: name = VDD exists, forcing drivepoint Location is (634, 1312); drivepoint (634, 1312) Port: name = VSS exists, forcing drivepoint Location is (626, -19); drivepoint (626, -20) Port: name = out exists, forcing drivepoint Location is (936, 420); drivepoint (936, 420) Port: name = in exists, forcing drivepoint Location is (249, 422); drivepoint (249, 422) Missing substrate connection of device at (626 220) on net VSS Missing substrate connection of device at (626 220) on net VSS Total Nets: 4 Nets extracted: 4 (1.000000) Nets output: 4 (1.000000) %

That's not, strictly speaking, an error. Updating magic should (I believe) get rid of the "missing substrate" errors. However, the extraction is still valid, with a slightly less accurate substrate network.

I corrected my test bench file but as such the inverter is not working, do you know what could be the cause?

@Juan Andres: It works if I correct the voltage source in

inverter_blo.spice

from

VDD net1 GND DC{vdd}

to

VVDD VDD GND 1.8

and I correct the ground pin in

x1 out in VDD VSS inverter

to

x1 out in VDD GND inverter

.

Yes, thanks