inv_2_scm.spice,inv_2_scm.mag

Do you understand the well/substrate problem? The standard cells do not individually have well and substrate contacts. Those exist in tap cells. If you want to hand-generate a layout with standard cells, you must have at least one tap cell in every logic row every 15um. For a single standard cell, you will still need a tap cell next to it.

@Tim Edwards @Mitch Bailey Excuse me, I want to clarify the issue i found. Because i have an updated machine instead of using ciic machine. 1- i extract as simple standard cell (inv_2) from xschem as shwon in Fig.1 with netlist nammed

inv_2_scx.spice

2- i extract the spice file of inv_2 layout from Magic as shwon in Fig.2 with netlist nammed

inv_2_scm.spice

3- use net-gen for LVS

netgen -batch lvs "inv_2_scm.spice inv_2_scm" "inv_2_scx.spice inv_2_scx" /home/ahmedreda/PDK/sky130A/libs.tech/netgen/sky130A_setup.tcl

4-I got that LVS is failed as in

comp_out

as in Fig. 3 Thanks in advance.

@Ahmed Reda: (1) Your schematic-derived netlist has only a call to

sky130_fd_sc_hvl__inv_2

and does not define what it is or what its contents will be, or what its pins are. The layout netlist has the contents down to the transistor level, and has pins for the

inv_2

subcircuit. You are giving netgen no information on how to compare those cells. As Mitch said, you need to include the HVL SPICE library from the PDK in your schematic (by an "include" statement in a code block). (2) Your

A

and

Y

pins in your layout have no contacts down to local interconnect, so the pins aren't connected. Checking connectivity in magic is trivially easy, so there's no excuse for having things unconnected. (3) Drawing custom layout around standard cells is dangerous because the layout does not always match the GDS data. In this case it's probably okay, but it would have been both safer and easier to just place a tap cell next to the inverter cell. (4) Also, related to (3), a decap cell would be a good idea in a custom standalone digital circuit, and if it's for an analog or mixed-signal system, the whole thing should be placed in a deep nwell structure.

@Tim Edwards @Mitch Bailey Thank you for your patient. The issue is fixed by including the this line to the extracted file from XSCHEM.

.include .../PDK/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice

I was thinking the XSCHEM can define the spice of standard cell by default. Thanks.

@Ahmed Reda: Magic extracts this as a diode (SPICE type

D

) while xschem is extracting it as a subcircuit (SPICE type

X

). The sky130 model definition is a diode, not a subcircuit, so the xschem symbol needs to be corrected to output

D

, not

XD

.

Thanks. I got It.✅