open-source-silicon.dev

inv_2_sc.spice

comp.out

<@U016EM8L91B> <@U017X0NM2E7> Excuse me, I was trying to pass LVS of one of a standard cells  such as simple *`inv_2`* on my machine. However, I found this mismatch report. can you suggest me to fix it, please?
By the way, i used `netgen -batch lvs "inv_2_scm.spice inv_2_scm" "inv_2_sc.spice inv_2_sc" /home/ahmedreda/PDK/sky130A/libs.tech/netgen/sky130A_setup.tcl`

<@U03ED7UNVFH> you need to include the standard cell spice.

You probably don’t have well/substrate contacts in the layout either.

<@U017X0NM2E7> which  and where file should i update it, please!

image.png

I suppose this error need to adding standard cell spice right!

<@U017X0NM2E7> so which file should i change to fix it?

```netgen -batch
read spice $::env(PDK_ROOT)/$::env($PDK)/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice 1
lvs "inv_2_scm.spice inv_2_scm" "inv_2_sc.spice inv_2_sc" $::env(PDK_ROOT)/$::env($PDK)/libs.tech/netgen/$::env($PDK)_setup.tcl```
That’s just a quick guess. I haven’t tested. You’ll still get the substrate/well mismatches.

I see and It is easy to fix substrate/well mismatches.  I will try your batch.