Hi, I have been reading about cell design and I am curious about something that is not mentioned (I guess the answer is implicit or obvious, but I would like to rectify why, because I am not sure and I am learning this by myself), In all the figures I have seen from books, all the mosfets are symmetrical, but they only paste the picture of the inverter or simple cells or others just show very simplified diagrams with all the diffusions with the same size. On the other hand, looking at sky130 cells, I have seen some with one or two mosfets with different diff sizes [Fig 1 ] but most are symmetrical. And that 's my question, what is the problem if my mosfets are not symmetrical? [Fig 2] Is it mandatory to have same diff sizes?

Good question. Googling

nmos pmos drive strength

gives a bunch of answers. Here’s one

The drain current of a mosfet is proportional to mobility and the ratio w/l.

Electron mobility is typically 3-4 times that of a hole.

So to have comparable drive power, the sizing (in an inverter) is done such that the lengths are the same, but the width of PMOS is 3-4 times that of NMOS.

David, thanks for answering. I did a lot of simulations to find the optimal Wn and Wp so the trise and tfall were equal, I got a difference of approx 1.83 ps testing those Widths in an inverter under tt corner, using sky130 mosfets (primitives). Now your answer gives me one more question, was my calculation tied to the same Lp and Ln? I'll check that tomorrow. If that is the case, it would be interesting to find a methodology where I can find not just a Wn/Wp relation, but also a relation between those ratios W/L.

Generally, the length of the source or drain region isn't considered part of the "symmetry" of the device, although of course the longer terminal area will have a bit higher resistance. That will affect the pull up/pull down characteristics of the transistor stacks. But it won't affect it so much that it would be an overriding consideration to make all device terminals exactly the same. In this case, other considerations are more important, such as total area of the cell, keeping the gates aligned (which avoids troubles with poly-to-poly spacing), and fitting multiple contacts were possible (because these contacts are quite high resistance, as much as ~300 ohms per contact). Ultimately, if there are multiple competing trade-offs, the final design will be the one that maximizes speed or minimizes area or whatever the specific standard cell library is trying to achieve.

There are some applications (e.g. encryption) where you want perfectly balanced behaviour, I heard about a factor of 2.7 to be the best, to avoid side-channel attacks.

@Philipp Gühring: Nelson was marking the source/drain areas, so he was talking about terminal length, not gate width.

When a circuit has two or more transistors in series, you get the best result if they get wider and wider as you go from the output to the ground (or supply in the case of pfets). You can see this in custom designs, but for standard cells this optimization is not practical

That's it @Tim Edwards, thanks everyone.