Hello everyone, I would like to know if there is an specific reason for these widths of VDD / VCC rails into the sky130 standard cells. I checked several cells and all of them have these dimensions. If I want to design my own cells, I have to repeat these widths too?

Size and placement of standard cell abutment-boxes is limited to a grid https://antmicro-skywater-pdk-docs.readthedocs.io/en/latest/contents/libraries/foundry-provided.html, for single-row

_hd_

standard cell abutment-boxes the height is 8x0.34=2.72um with width Nx0.46um where N is an integer. If you look at your measurements, then 0.145 is half the size of a via distance 0.29, and via size 0.17 with via distance 0.29 adds up to one X-GRID unit width 1x0.46. This limitation allows DRC-error-free placement of abstracted standard cells left and right, above and below, mirrored, rotated, and the power rails will always align with the rails and vias of the abuting standard cells

@SUMANTO KAR excuse me, could you give me more context about those screenshots?

@Nelson Rodriguez yes, sorry I didn't describe them. These are the snippets of the sky130A.tech file. So, here they have mentioned the minimum lengths and areas.

@SUMANTO KAR @Manuel M I was measuring the pitch for metal 2, but I'm confused with the dimensions you pointed me (

0.29 um

), the width tracks should be separated by that 0.29 um or by 0.40 um?

@Nelson Rodriguez please check the peripheral rules https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html

I don't know if or why the power-rail vias (mcon) have something to do with metal2 pitch. To me it looks like the metal2 pitch is not the reason why the standard cell grid dimensions have been chosen, but I can only make assumptions. Example where the smallest allowable mcon distance can make problems: See this image from a

_hd_

design, i have deleted some cells in the middle. It is not possible to to fit your custom cell anywhere in the empty space of a

_hd_

design without creating DRC errors if the power rails do not match

@SUMANTO KAR Sir you're right, but I was looking for the meaning of

areaid.ed

do you know what does that mean?

These are all drc tags and can be found here: https://github.com/google/skywater-pdk/blob/main/docs/rules/periphery/periphery.csv

If you mean that the metal on the power rails should be wider, it's because these rails have substantial current running through them compared to signal wires, and they need to keep resistance low to avoid I-R drop between the points where the standard cell row connects up to the power grid. Generally, you want to make the power rails as wide as you can, but it's a trade-off because the wider they are, the less room you have for horizontal signal routes on the same layer. The sky130 process has an additional concern that you may not find in any discussions of standard cells, which is that they have this layer called "local interconnect" which is made from titanium nitride (TiN), which has a resistance about halfway between polysilicon and metal. The local interconnect is what connects directly down to the transistor sources and drains, but because it is relatively high resistance, you don't want to use it for the power rails. So the power rails are strapped across the entire length up to metal1.

@Nelson Rodriguez the .tech file and the .periphery rules file are the best ones to find out...

@SUMANTO KAR Thanks for your answer. I've been checking in the rules but I still have some doubts about the min length of those mcon on the power rail. I've searched

0.29

in the link you gave me (https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html#hvdifftap), but I think, any of the 3 results are related to that rule. [Fig 1] Could you please help me? And also, I was trying to find the doc where you took this screenshot [Fig 2], but I couldn't, please could you share me the link? @Tim Edwards @Manuel M could you help me too with that search?

@Nelson Rodriguez I think difftap and hvdifftap follows what you are saying

@Nelson Rodriguez: The box labeled 0.29um in your original post is the space between two contacts, and is larger than the minimum contact spacing. The spacing is presumably dictated by the standard cell unit area and the need to have contacts that are equally spaced when cells are exactly abutting.

@Tim Edwards it means that in the same way I can choose the Y-GRID, as long as I respect the design rules [Fig 1], I can also for the X-GRID, in which the minimum spacing between mcon is

0.17 um

[Fig 2], so

0.29 um

is not mandatory?

The minimum spacing between MCON is 0.19um. With the MCON width of 0.17um, that makes a minimum pitch of MCON of 0.36um inside of a metal1 area. But MCON has to be surrounded by metal 1 by 0.03um on all sides. If you wanted to be able to drop unconnected MCON contacts in two adjacent route tracks, you would need a minimum metal1 pitch of 0.37um. By enforcing that you cannot have MCON in adjacent tracks, you can reduce the metal 1 route pitch to 0.33um (the HD standard cells have a metal1 pitch of 0.34um; I'm not entirely sure why it's 10nm more than the minimum).

I draw your indications [Fig 1] but @Tim Edwards what about via1? Does routing make use of met2 isn't it or not? I have that doubt, because when I saw the info about Y-GRID [Fig 2] I supposed that routing was made with met1, because the min dimension of a via1 is

0.26um

. On the other hand, could I argument that cells using a X-GRID of

0.46um

is better than using

0.36um

because less contacts are used (so less material used)?

There are certainly good reasons why a larger pitch can produce better routing than the minimum pitch, but I wouldn't necessarily conclude that without careful study, and running a lot of test examples.

This thread made me curious why it actually is 0.34um and 0.46um for

_hd_

. I evaluated a hardened design and it looks like the pitch for metal1 is differently calculated than the pitch for metal2. Metal1 uses track-via distance (no adjacent vias) and metal2 uses via-via distance (adjacent vias). My guess: X-GRID is minimum 0.46um because of the metal2 via-via pitch for easier routing. With this limitation and mcon vias with 0.17um width, the residual width at the mcon vias would result in 0.29um

Okey @Tim Edwards I'll read more about that. Thanks @Manuel M your images are very very useful, I'm interested in tool you're using, is it klayout?

magic

and the second image is from

OpenRoad