@Tim Edwards I'll try again with the latest versions of the programs and files, and post pull requests for the relevant repos. Wanted to get something working first. Right now, I'm using branch mpw5a of

caravel_user_project

for openlane and updating to the most recent version of openlane requires changes to deal with a different directory structure (previously

<design>/run/<tag>/results/lvs/files

currently

<design>/run/<tag>/finishing/<files>

or something similar). Changes to

chip_io

layout should be directly to gds, correct?

The logic analyzer inputs are supposed to be allowed to be open under the condition that any C program driver leaves the inputs in the disabled state.

Are you saying that the logic analyzer can handle Hi-Z inputs? I haven't had much experience with verilog or logic simulation, but what I see is Hi-Z inputs to buffers which can result in leaks because both pmos and nmos are not off. Now whether or not 100+ floating inverter inputs generate enough leak current to effect the operation of the chip probably depends on the design.