# lvs

Tim Edwards

02/28/2022, 2:40 AM
No, I mean that for signals coming from the user project to the logic analyzer, there is an AND gate ANDing the input with the input enable, so that if the input enable is low, then the input signal can be floating. Or at least that's the way it's supposed to be. I keep having issues with the Openlane team configuring the tools to insert buffers where there shouldn't be any. I thought I sorted that out with the gate level netlist for MPW-four, but if you think it's misconfigured, I'll take a closer look at it.