Slot-019 of mpw4, looks like there may have been some synthesis problems with the inputs. In the rtl,

multiplier MULT(
`ifdef USE_POWER_PINS
        .vccd1(vccd1),  // User area 1 1.8V supply
        .vssd1(vssd1),  // User area 1 digital ground
`endif
.clk(user_clock2),.input_a1({io_in[15:0],io_in[15:0]}), .input_b1( {io_in[31:16],io_in[31:16]}), .product(la_data_in[31:0])   );

endmodule       // user_project_wrapper
`default_nettype wire



(* blackbox *)
module multiplier(input clk, input [31:0]input_a1, input [31:0]input_b1, output reg [31:0] product, inout vccd1, inout vssd1);
endmodule

but in the gl

multiplier MULT (.clk(user_clock2),
    .vccd1(vccd1),
    .vssd1(vssd1),
    .input_a1({_NC1,
    _NC2,
    _NC3,
    _NC4,
    _NC5,
    _NC6,
    _NC7,
    _NC8,
    _NC9,
    _NC10,
    _NC11,
    _NC12,
    _NC13,
    _NC14,
    _NC15,
    _NC16}),
    .input_b1({_NC17,
    _NC18,
    _NC19,
    _NC20,
    _NC21,
    _NC22,
    _NC23,
    _NC24,
    _NC25,
    _NC26,
    _NC27,
    _NC28,
    _NC29,
    _NC30,
    _NC31,
    _NC32}),

input_a1[15:0]

and

input_b1[15:0]

of multiplier are flagged as HiZ inputs.