It is most likely way too early what I was thinking about, but let me share it: I assume that the Min Clock High Time is a parameter for the SRAM, as it appears in the timing checks (although it will be rather small and eventually not relevant). For sure it has been evaluated during simulation already. With the “write-read-same-address” silicon test above, I assume that this parameter can already be characterized by modifying the duty cycle (reducing Clock High Time) and can be then compared to simulation. Min Clock High Time will probably be so small that our designs will be limited by other aspects (clock tree dynamics). But some crazy folks might shift the neg edge to make up for path delay. What do you think about it?