since I do various things on the rising or falling edge

It would be possible to change this with some funky PLL configuration on the FPGA I think, but I'd have to think very carefully about that to make sure I don't break anything in the test firmware

Static timing analysis on the FPGA side is nontrivial when you add partial reconfiguration of the PLL in, because the PLL config that the timing analyzer runs on is not the same config that is present at run time

so all of my clocks are shifting in frequency and phase

@User I sent you an email

@User BTW 2 trays is 8x8x2 == 128 tiles. Is that too many?

I mean, for basic imaging I only need one die. For deprocessing I'd like a few to experiment with. One tray is probably sufficient

honestly even that is likely overkill, I can send back any that I don't end up doing any processing on

@User Got the samples. The package is a bit annoying without a sealed top

But I'll make do

Will likely end up repackaging into another form

@User By sealed top, you mean the little plastic case?

I like gel packs or trays with top covers

so i can put it on a shelf under more samples, or bump the table without them flying everywhere, etc

the open top tray with nothing holding the dice in place requires much more care in handling and storage

@User have you posted schematics of your test setup anywhere? One question I was thinking while looking over the data is how the FPGA interfaces with the RAM during read/write (or vice-versa) as you shmoo the voltage. For example on the Jan 10 plots when the voltage is 1.4V (Maybe VCCD?) what is the voltage on the bank of the FPGA IO block? also 1.4V? The higher level question that I’m alluding to is, are you sure the skew between bits was maintained as voltage was varied? Just floating a theory as to why those fails might be frequency dependent.

@User KiCAD design files are at https://github.com/azonenberg/sky130-validation/tree/master/or1/boards

The DUT I/O pad ring, microcontroller, and FPGA I/O rail all run at a constant 3.3V

We only change the 1.8V nominal domain feeding the DUT core

This affects the SRAM cells, row/column circuitry, any buffering or top level logic between the SRAM IP and the I/O cells, and the internal side of the I/O pad drivers

the other voltage domain of the pad driver is constant

if there is skew variation, it's likely on die in the routes between the SRAM IP and the I/O cells

Which I'm told is quite long and predates proper top level STA

@User Are your images of the test tiles in an archive somewhere?

@User Finding the tweet on Twitter keeps getting harder, so it would be good to put them somewhere

@Kennedy Caisley has left the channel

People here might be interested in a recent presentation that Antmicro did at the ESSCIRC workshop about "Pre-silicon testing of SkyWater MPW designs using co-simulation with Renode and Verilator" found @ https://docs.google.com/presentation/d/e/2PACX-1vT2pOMi-crvIhns7ulGvmvDdFy7pGb0L28kJouSnseVHl4fHugabSz5yLD5ocU7CfaTtNVSWDyJwl9b/pub?start=false&loop=false&delayms=3000

Sorry, that URL should have been https://docs.google.com/presentation/d/e/2PACX-1vT8OYu5lkpaHLJeBu07BFR-3u88vtRHOnKsIBAVSk4gLCa3-GaDWUny1XQ_rEJxaMJgl6LbmtbBXayc/pub?start=false&loop=false&delayms=3000

Hi all, I taped out a bandgap reference circuit in college and got to measure one silicon sample with @Eric Smith after I graduated. Ideally I would have more samples but nevertheless I want to share the data. Data is in a github here. Silicon data is shown in plots in the README. Raw data (csv) and scripts used to make plots are in

silicon_measurements/

The (limited) data shows a discrepancy between layout-extracted circuit simulation and measured silicon. The discrepancy is in the temperature coefficient of reference voltage output (see github: Output reference voltage vs. load and temperature and table: design goals vs. post-layout, extracted circuit performance). The discrepancy in temp co is 3.6 ppm (simulated) vs. 137.6 ppm (measured). Quite different. My initial approach would be to dig into the BJT circuit model and investigate what could have caused this large difference. Iterate over (relevant) BJT model parameters, modify each one, and observe how each change either moves or doesn’t move the tempco from 3.6 ppm to 137.6 ppm. I am curious to hear the channel’s thoughts on what could be the source of this performance mismatch. I’m hoping someone else has the time and interest to help find the answer. I think this could be a nice learning opportunity for myself but I just started graduate school and I fear I will forget about this question; sharing the question with you all helps me stay interested in answering it 🙂