@User: Thanks, I read about that in the Yosys and ABC documentation. I was investigating Yosys techmap modifications to see if I could get smaller adders, etc. but it isn't that straightforward. A simple ripple carry would be too slow, and I know the commercial synthesis tools to some pretty wicked optimization using a combination of full / half adders plus carry lookahead. I was also thinking of an optimized multiplier compiler (with programmable width, pipeline, round / saturation, etc.). But that would be a bigger project. I have a 16-bit processor I wrote in 1998 that I have used over the years, and I have pulled it into the Openlan flow and have a GDSII. I was able to modify the synthesis strategy to remove 1K cells relative to the standard SYNTH_STRATEGY=2 setting. My processor is less than 8K cells with 16 GP registers, hardware multiplier, profiling and debugger! But I am adding a few extensions to the ISA, so it may grow slightly.