GitHub
12/27/2021, 4:38 PM*.sp
to *.lvs.sp
because *.sp
doesn’t have the correct memory cell parasitic devices.
Changed l
and w
units from meters to micrometers.
Reversed bus order in sram top subckt pins.
The base code for creating the new file (error handling, etc.) was taken from other scripts in the same directory. Parameter scaling and bus reordering was added.
Error handling has not been tested.
Successfully passed LVS with the mgmt_core
module from <https://github.com/efabless/caravel_mgmt_soc_litex.git>
which contains sky130_sram_2kbyte_1rw1r_32x512_8
.
These changes should be all that are needed to allow the sky130_sram
macros to pass device level LVS (although the current version of netgen does take awhile).
RTimothyEdwards/open_pdks
GitHub Actions: Run (all)
GitHub Actions: Run (sky130_fd_sc_hvl)
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