@User It might come from the openlane flow.tcl. It chokes with the following debug message

"quit_on_illegal_overlaps -log [index_file $::env(magic_log_file_tag)_ext2$extract_type.feedback.txt 0]"
  (procedure "run_magic_spice_export" line 65)

It looks like the extracted netlist may be CVC compatible, so I'm going to start debugging the results. Is there any where I can get my hands on the schematics for chip_io or at least the cells used in chip_io? I looked in the skywater libraries, but could only find the verilog.