Any ` include` lines usually done using `code

Question

< U017UPJEGKZ> Any ` include` lines usually done using `code sym` symbols in xschem can be placed at lower level hierarchies thus not only in the testbench Adding a `only toplevel=true` in these code blocks the content will be dumped to netlist only if netlisting the schematic as a toplevel If netlisting a testbench instantiating a symbol of the schematic containing said code block this will be totally skipped if `only toplevel=true` attribute is present Another useful switch is in `Simulation gt LVS netlist top level is a subckt` This will wrap the top level schematic in a subckt ends declaration Some LVS tools need that