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Tim Edwards

03/02/2021, 2:05 PM
@User: netgen only knows what's in the netlists. If the schematic netlist has a ".include" statement reading the standard cell contents, then netgen will see it. But if the ".include" is in a top-level testbench schematic while a file containing only the subcircuit is passed to netgen, then netgen won't know about the contents of the standard cells on the schematic side. One solution is to make sure that the ".include" statements appear inside the netlist file that is passed to netgen (and that it points to a valid location, either an absolute path or a relative path relative to where netgen will be reading the file). Another solution is to set up a script for netgen where you read the standard cell libraries and the top-level netlist separately. I was setting this up recently for a caravel chip LVS. It would go something like this: Say you want to compare a layout extracted netlist
A.spice
subcircuit
A
against a schematic-captured netlist
B.spice
subcircuit
B
. But
B.spice
is just a subcircircuit, and to simulate it you have to include library files
B1.spice
and
B2.spice
which are not in the netlist file. Then you can create a script
my_lvs.tcl
to pass to netgen that looks like this:
set file1 [readnet A.spice]
set file2 [readnet B.spice]
readnet B1.spice $file2
readnet B2.spice $file2
lvs "$file1 A" "$file2 B" sky130A_setup.tcl comp.out
Then run
netgen -batch my_lvs.tcl
to run LVS.