@User I think for routing the VNB, VPB should be accessible via LI layer not the pwell or nwell? Can we modify the layout then add LI layer for those bias pins? Actually, this problem occurs in both openlane and Innovus. You can reproduce this error from our test cases on github https://github.com/FPGA-Research-Manchester/FABulous-SKY130 So, again the openlane flow got stuck when doing routing for our 4x4 (CLBs) fabric, it can only go through for some tiny designs (e.g. 2x2 CLBs), that’s why we use Innovus at the moment.