@User good job! Did you resolve your issues? Did my .lef file help by any chance?

@User Thanks but we used the sky130 original one for the antenna info

I'm currently trying to harden a design together with the user_project_wrapper in Innovus. For this I used the last generated .def file from the openlane floorplanning stage as an inital floorplan, so the physical io pins are already at the correct spot. But I have tried to remove the metal stripes accross the core are, because I want to generate them using Innovus (to create macro p/g rings blockages and using the already existing rings for large designs, etc.). My empty floorplan before any power routing basically looks like the in the snapshot. But I'm running into one problem after the other. I guess partly because of all the metal outside of the die area... My questions are, if the stripes I am generating with Innovus must be at the exact same position as if they would be generated by openLane, i.a. am I really allowed to remove those pins? And are those metal wires outside of the die even includes in the final .gds or are they actually merged from the caravel.gds? And also has anyone done this before or is it just utter nonsense and I should rather harden the design as a stand-alone macro and use openlane for the wrapper integration?

Hello everyone, I got an error message while working with the cadence innovus with sky-water pdk. How can I solve this error?

Hello, I have a couple of questions 1. Has there been any announcement of the sort whether we can take part in the shuttle program using cadence with sky130 pdk? 2. I just started with sky130 PDK, but I don't see any

*.cap

,

*.tch

or

*.map

files in there.

@User 1. I think they are looking for open source projects (source codes, design flow etc.) those required well documenting. 2. Not everything there but you can refer this repo https://github.com/FPGA-Research-Manchester/eFPGA---RTL-to-GDS-with-SKY130

Hello, during connectivity check, I have observed the that nwell are not connected to VPWR. @User @User Any ideas?

Hello, has anyone run lvs using innovus. It requires a rule file and I can't seem to find it anywhere. Thanks in advance

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Hello, I was using Cadence - Innovus to harden my design. It showed 0 DRCs in innovus, however as soon as I tried to insert it in the user_wrapper as a blackbox, Magic generated millions of DRC violations. @User Any insight of what could have gone wrong?

@User: What do you mean by "inserting it as a blackbox"?

I meant using my design as a macro inside the user wrapper area.

Can I ask why the followpin were not connected to the core ring and connected by stripes in the openlane flow.

Hi, I tried harden the user_proj_example in innovus and then used the lef and gds and then tried to integrate into the wrapper via openlane . During magic drc I am getting illegal overlap issues

I am not able to understand the cause and location of the issue

Hey @User the following 2 snippets are from Innovus and openlane. Innovus does not seem to know anything regarding n-well so it does not care about n-well spacing etc. which throws errors when I try to put my design in user_wrapper and run

run_magic_drc

. You mentioned "_the current technology LEF file does not define a cut layer from nwell or pwell to local interconnect, and so the contact isn't represented in the abstract view"_ Is it because of that. How do I resolve it then?

If you are generating the view on the right, then you need to be adding fill or decap cells to fill in the spaces, not just leaving them blank.

@User @User have you figured out how to fix the N/P-diff issues? I also hardened our macros with Innovus then encountered the same errors after ran the precheck.

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Has anyone performed the innovus design flow on skywater-130?

Hello, I have hardened my design using Cadence-Innovus. I am currently facing the issue of pin overlap. If I open the my design in klayout I see the IOs have 

pin layer

 but they are not enclosed by the 

drawing layer

 . However, I only see the met2 layer for IO placement in Cadence. There isn't any 

met2 pin layer

 or 

met2 drawing layer

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Hi guys, I might ask a silly question, while does anyone know can digital standard cells of double heights and digital standard cells of single height PnR together by innovus?

anybody has working setup of innovus with sky130 ? a basic setup just for PPA

I started with UCB Hammer's sky130 example using Genus and Innovus, but it violates the "Klayout minimum metal clear area density" DRC when SRAM is used. I've been unable to figure out a solution other than severe under-utilisation of the die area. Has anyone dealt with this?

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what is the equivalent Open source CAD of innovus?

Hi everyone, I am running innovus for Sky130 pdk using a riscv processor and openram generated sram memory. We are facing the following issue. Attached are both sky130_tech.lef files and sram_tech.lef files. Can someone help us out ?