After a frustrating couple of days, I'm ready for ask for help with my simple digital-only project from someone with more Verilog experience. I'm getting desired output from iverilog simulation, but in the real world I have... - a bus with multiple drivers that I can't seem to mux away correctly - reported inferred latches in Yosys - reported undriven wires in Yosys - the possibility I'm doing basically everything wrong