Hello everyone, I am trying to do pre synthesis simulation and post synthesis simulation of 8 bit counter. And using tools For simulation iverilog For synthesis yosys and standard cells verilog models from sky130 I am getting perfect results for pre synthesis simulation. But when I am trying to do post synthesis simulation output is 'x' The following is the link where I have kept in three folders 1. pre-synthesis simulation, which I am getting 2. synthesis folder where i have done synthesis using yosys 3. post-synthesis simulation, which I am not getting https://drive.google.com/file/d/1iVb8iZ85-nPuvsS5HyK-0hpmGh9dteSx/view?usp=sharing Please help.