There are other nice things that can be done, for example a netlisting rule can be given for verilog (really simple, a one-liner for combinatorial and a few lines for flops) so a circuit can be simulated at the functional level (clearly no exact matching of gate delays)...if there is interest i can start the job, i just need to know what do people need more for standard cells. If there are already verilog library files let me know i will try them...