Hello All, I'm looking for some recommendations on how best to compose a design from macros. It seems there are basically two approaches at the top (core) level:
• Top-level synthesis at the core level (no std cells). Macros are just wired together
• Normal synthesis at the core level, with ability to introduce some logic
Is one approach preferred over the other?
With no std cells at the core level, I'm able to go through the flow mostly cleanly. I'm still encountering an LVS error around power pins (more later). However, I can see that macro pins that are not wired to another macro pin are left truly disconnected. Will this be an issue for SRAM cells, for example?
With std cells at the core level, I receive some DRC errors within the macro area, with the 'nwells must be connected' seeming more concerning.
Anyway, any advice on which approach I should pursue would be much appreciated!