12/06/2021, 1:31 PM
VSD-HDP - Top RISC-V and Sky130 Analog projects Many of you requested top high visibility HDP projects and training, which directly opens up job opportunities. So here are top RISC-V and Analog design projects, which you can enroll in and learn from scratch. VLSI training is no more tool training, but real-time project work- a classic top-down approach done in industries, where you start from a project, infer the tools needed to execute the project and get trained on them. VSD has expertise in this approach for close to 4 years now, and most of VSD-HDP students are doing amazing in industries. RISC-V: 1) Visualization of SweRV {Project code - VOS} - The SweRV core is an open-source SystemVerilog RISC-V CPU core developed by Western Digital. It is an interesting core for college course and is being highlighted in the RVfpga course for one. Visualizing the operation of the core can greatly enhance the learning experience. This project aims to do so. SweRV is be built and simulated within Makerchip 2) Implementing other ISAs in WARP-V {Project Code - IIW} - WARP-V currently has support for RISC-V, (incomplete) MIPS, and a toy educational ISA. PowerPC is also open now and could be implemented, in addition to any other open ISAs. 3) Neural Net {Project code - NN} - We have created a simple configurable neural network model in TL-Verilog. This could follow a similar path to WARP-V w/ a configurator and cloud FPGA implementation. The WARP-V configurator is build in a modular fashion to support this easily. Analog: 1) High Frequency analog VCO design and implementation using Sky130 {Project code : KCEDVCO} 2) Low Dropout Regulation using Sky130 :A low-dropout regulator (LDO) is a DC linear voltage regulator that can regulate the output  voltage that is powered from a higher voltage input. {Project Code:LDO} Here's your chance to work closely with industry mentors and industry teaching assistants, while getting trained with the right approach. Look for more sky130 based projects on backend, frontend, verification, EDA and FPGA in below link (Last 5 days)