12/10/2021, 5:44 AM
Last 12hrs - Top Sky130 Back-end and FPGA projects for VSD-HDP Over the last few years, online/offline VLSI training has taken a whole new angle, and the demand is more for the latest industry project based training. Thanks to VSD industry partners for floating their projects with VSD as a part of a 10-week HDP program. Training is now like industry grade design projects. There was a thin line between the design industry and training institutes which is diminishing . So let's welcome this change whole-heartedly One of our previous HDP students made the above flyer for VSD, characterizing the whole VSD-HDP process for freshers and professionals. Take a look at the flyer as this describes exactly what's done at VSD-HDP. The registration for the next cohort expires in the next 12-hours. Here's the registration link- Here's the list for top Sky130 backend and FPGA projects. There are other analog, RISC-V, frontend, verification and EDA projects listed in above HDP link Backend 1) rvmyth integration with PLL, DAC and SRAM using Sky130 {Project code - RPDS} RISC-V based SoC design, implementation and tapeout using VSD Sky130 IPs 2) Performance characterization for VSDBabySoC comprising of RISC-V core, PLL and DAC {Project code - PCVRPD} Analyze and characterize RISC-V based VSDBabySoC for all timing corners, fix timing violations, ECO, implement and tapeout rvmyth : RTL2GDS with OpenLane with the standard cells from 3) Libresilicon StdCellLib generated standard cells for SKY130 {Project Code:ROLS} Take the LibreSilicon Standard Cells for the SKY130 process and synthesize a RVMYTH design using those standard cells with OpenLane, preferably directly into an EFabless Caravel User-Space. FPGA 1) 1st CLaaS for Local FPGAs {Project code - 1CLF} 1st Class supports web application communication with FPGA logic in the cloud. Support local FPGA use cases as well. This is useful for local applications as well as to support development that will ultimately be deployed to the cloud. 2) World CLaaS: Open FPGA Cloud {Project code - WCOFC} The vision is to enable individuals with FPGAs (World CLaaS Citizens) to share their hardware with the world 3) WARP-V Many-core Accelerator Microservice {Project Code - WMAM} It will provide a configurable, easily-modifiable many-core-on-FPGA hardware accelerator deployed as a microservice to accelerate web and cloud applications. All the best and happy learning