@User You can explain most of the difference between this approach and looking at inverter performance using 2 factors: lower gate capacitance because they are using smaller n-channel transistors for the heavy lifting, only needing 2 not 3 stages because it is differential. With inductors you can get to 12GHz: https://eprints.soton.ac.uk/403706/1/__filestore.soton.ac.uk_users_skr1c15_mydocuments_eprints_ECS_Ke%2520Li_Analysis%2520and%2520Implementation%2520of%2520an%2520Ultra-Wide.pdf sky130 has dual Vt so the schemes in this 5GHz CPU from 2002 in 130nm should be readily achievable with custom layout. This will be hard to achieve with the standard cell libraries. http://www.ee.virginia.edu/~mrs8n/conf/01046084.pdf Another metric is D-flip flop delay. This is a nice recent survey paper of that with various designs including 130nm as a starting point: http://www.warse.org/IJETER/static/pdf/file/ijeter86852020.pdf