<@U016EM8L91B> <@U01EYE54L5N> the offending standa...
# analog-design
s
@User @User the offending standard cell is the first one in the inverter.spice netlist, it's a decap cell, containing p an n fets (p with gate to gnd, n with gate to vpwr) :
Copy code
.subckt sky130_fd_sc_hd__decap_12 VGND VNB VPB VPWR
X0 VPWR VGND VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=870000u l=4.73e+06u
X1 VGND VPWR VGND VNB sky130_fd_pr__nfet_01v8 w=550000u l=4.73e+06u
.ends
since these do not take any parameter either the standard cell is wrong or the model binning is wrong.