Stefan Schippers
11/09/2020, 8:54 PMclock
* a5 1 8 var_clock
* .model var_clock d_osc(cntl_array = [-2 -1 1 2]
* + freq_array = [1e3 1e3 10e3 10e3]
* + duty_cycle = 0.4
* + init_phase = 180.0
* + rise_delay = 10e-9
* + fall_delay = 8e-9)
** stefan added a pulse generator don't know much about above syntax and it does not appear to connect to "in" node
vpulse in 0 pulse 0 1.8 0 1n 1n 9n 20n