On some example layouts for other PDKs I am seeing all the vias implemented as a groups of minimal size-ish square vias. But on the transistor generator for the sky130 pdk I see it creates a single long rectangular via. There seems to be no explicit DRC rule against such vias, but even on the foundry provided layouts, such as the IO pads, I am seeing all the vias implemented as arrays of small rectangular vias. Is there any reason to avoid such long rectangular vias, or is anything that does not violate a DRC rule good?