Faedra Webers

08/27/2022, 4:59 PM
Hello , I'm making a 10b SAR and have some questions involving the power consumption of the digital cells. I connect a 'clk_comp' signal and 'clk_switch' signal to an AND gate which is BUFFERed to clock the comparator. Another OR gate creates the clock of the logic based on the comparator output. I'm confused as why there is a current peak in all three blocks at the same moment when clk_comp and clk_switch rise (as seen in current_peaks.png) when the input signals of the BUFFER (clk_comp_and_check) and OR(vop & von) gate don't change at that moment. They all have different supplies, which are only connected to these digital gates. vvccc = BUFFER, vvcccq = AND , vvccct = OR. I implement this so that my comperator would not switch during the sample phase with the goal to save power. For calculating the power, I do this by intergrating current and calculating oversum and undersum and averaging. The under and oversum start to converge around a timestep of 0.000001n which takes awefull long to simulate. Is there a possible work around to simulate the power faster? In attachement, the picture of the waveforms and spice, raw, output and sch file. Have a nice day Kind regards Faedra