<@U03DNPRUBFD> your input clock signals (clk_comp,...
# analog-design
@Faedra Webers your input clock signals (clk_comp, clk_switch and also reset_b) have 0.1ps rise and fall time. This is unrealistic, you never will be able to get such rise/fall times on sky130. Use 0.1ns as rise/fall times. Having a almost ideal square wave as input to a gate will cause huge current spikes due to the gate capacitance of the gates. I = dV/dt *C. If the voltage derivative is very high you get huge currents. Check this modified schematic (you probably need to adjust the clock timings due to the 0.1ns rise / fall times) Added also .option method=gear to smooth the current waveforms and changed the timestep in tran line to 0.05ns.
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