It seems that there is a minor different between the caravel RTL netlist and caravel gate level netlist:

caravel/verilog/gl/caravel.v:3483: error: port ``la_oen'' is not a port of mprj.
caravel/verilog/gl/caravel.v:3483: warning: Port 16 (analog_io) of user_project_wrapper expects 29 bits, got 31.
caravel/verilog/gl/caravel.v:3483:        : Leaving 2 high bits of the expression dangling.
caravel/verilog/gl/caravel.v:3512: warning: input port clock is coerced to inout.

In the RTL, there are 'la_oenb' ports but in the gate-level netlist, they are named 'la_oen'.