Registration for RISC-V Workshop closes in 15Hrs https://www.vlsisystemdesign.com/riscv-based-myth/ Get ready for another power-packed high intensity, lab oriented RISC-V ISA simulation and RISC-V CPU RTL coding workshop using TL-verilog All the best and happy learning. Next workshops will take this RTL code further to Synthesis, PNR, DRC, LVS till GDSII