I’m experiencing a weird problem trying to run my gate-level tests (

verify-[test]-gl

). The simulation starts up and runs just fine, but only for a few thousand clock cycles, when it suddenly dies. I have no Idea why. I looked through stuff in GTKWave for a while, and can’t find any cause for this. It just happens. Top-most signal is the clock generated in the testbench, all others are from the design.

when you say 'dies' are you talking about the signals becoming x ?

Yes. This happens everywhere. Almost every single signal I can look at in GTKWave becomes invalid (x). The simulation is effectively stuck in that state, and such "dead".

the only time I've seen this is when the firmware is too large and the processor starts reading undefined values and then everything becomes undefined

The firmware just sets up the I/Os, and then ends with a

while(1);

and it works with RTL sim ?

Yes

I'd be interested to see the power supply & flash traces

Power supplies are fine everywhere I’ve checked. You can already see two of the flash signals in the screenshot.

It's interesting that csb goes x first. Tracing x propagation is a pain. But you could try to trace back that signal to find out where it's starting

Usually this happens: 1. (as Matt wrote) when reading undefined content of a memory. 2. Sampling some input signal that is not assigned. the 'X' rapidly propagate everywhere. 3. If it is a setup timing violation you can try at lower frequency. 4. If it is a hold violation you need to find out where the violation happens. Lowering the frequency doesn't help.

Okay, after an hour of tracing the x, I got all the way to

wbs_dat_o

of my design.