My target is to interface my design with this Caravel User Project, 1) So Can you send me a tutorial, etc, (How to do it maybe ) 2) How I can do the simulation because Caravel User Project is RISC V So I need to write the C language for RISV V and this processor will accelerate my design (Verilog)? 3) Can we do the simulation using Caravel user project but without interfacing with RISC V ? Do they free Tapouts without interfacing with the RISC V ? because if we do the simulation using RISC V we have written the C language code. (Guidance material)

https://github.com/efabless/caravel_user_project/blob/main/docs/source/index.rst#overview document

Thanks.

its an reference video. But try to use MPW-8 tag

I have already installed Openlane, I just modified the user project, according to the video and copied that folder into the openlane>design folder , and tried to simulate from that folder, is it necessary to add MPW-8 tag?

you need netlist and source RTL to run simulation and caravel has basic testbench format to verify

I only have the RTL, and yes I have modified the testbench, All steps are completed after ( Add custom test from above vedio) ( not before)

https://github.com/efabless/caravel_user_project/blob/main/docs/source/index.rst#section-quickstart this way all required things install automatically. Maybe you're missed something

make PDK will going to install all the PDK again I think, But I already have installed PKD? second Yes. Now I change the Tag to mpw-8c , Do I need an updated openlane too ? your suggestions Which one is better? I know the stable version is mpw-6b ,,,, but I did don't find mpw-8c , openalne

just clone latest commit and proceed

How to check the install version of openlane

thanks.